HCNW3120#300 Avago Technologies US Inc., HCNW3120#300 Datasheet
HCNW3120#300
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HCNW3120#300 Summary of contents
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HCPL-3120/J312, HCNW3120 2.5 Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description The HCPL-3120 contains a GaAsP LED while the HCPL- J312 and the HCNW3120 contain an AlGaAs LED. The LED is optically coupled to an integrated circuit with a power output stage. These optocouplers are ideally suited ...
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Selection Guide Part Number HCPL-3120 Output Peak Current ( I ) 2.5 A O IEC/EN/DIN EN V IORM 60747-5-2 Approval (Option 060) *The HCPL-3150 Data sheet available. Contact Avago sales representative or authorized distributor. Ordering Information HCPL-3120 and HCPL-J312 are UL recognized with 3750 Vrms for 1 minute per UL1577. HCNW3120 is UL Recognized with 5000 Vrms for 1 minute per UL1577. Option Part RoHS Non RoHS Number Compliant Compliant -000E No option -300E #300 HCPL-3120 -500E #500 -060E ...
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Package Outline Drawings HCPL-3120 Outline Drawing (Standard DIP Package) 9.65 ± 0.25 (0.380 ± 0.010 TYPE NUMBER A XXXXZ YYWW 1.19 (0.047) MAX. 3.56 ± 0.13 (0.140 ± 0.005) 1.080 ± 0.320 (0.043 ± ...
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Package Outline Drawings HCPL-J312 Outline Drawing (Standard DIP Package) 9.80 ± 0.25 (0.386 ± 0.010 TYPE NUMBER A XXXX YYWW 1.19 (0.047) MAX. 3.56 ± 0.13 (0.140 ± 0.005) 1.080 ± 0.320 (0.043 ± ...
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HCNW3120 Outline Drawing (8-Pin Wide Body Package) 11.15 ± 0.15 (0.442 ± 0.006 HCNWXXXX YYWW 2.54 (0.100) TYP. 1.78 ± 0.15 (0.070 ± 0.006) HCNW3120 Gull Wing Surface Mount Option 300 Outline Drawing ...
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Solder Reflow Temperature Profile 300 PREHEATING RATE 3 ° °C/–0.5 °C/SEC. REFLOW HEATING RATE 2.5 °C ± 0.5 °C/SEC. 200 160 °C 150 °C 140 °C 3 ° °C/–0.5 °C 100 ROOM TEMPERATURE ...
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Regulatory Information Agency/Standard Underwriters Laboratory (UL) Recognized under UL 1577, Component Recognition Program, Category, File E55361 Canadian Standards Association (CSA) File CA88324, per Component Acceptance Notice #5 IEC/EN/DIN EN 60747-5-2 Insulation and Safety Related Specifications Parameter Symbol Minimum External L(101) Air Gap (Clearance) Minimum External L(102) Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance CTI (Comparative Tracking Index) Isolation Group ...
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All Avago data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insula- tion requirements. However, once mounted on a printed circuit board, minimum creep-age and clearance require- ments must be met as specified for individual equipment standards. For creepage, the shortest distance path along IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics Description Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤150 V rms for rated mains voltage ≤300 V rms for rated mains voltage ≤450 V rms ...
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Absolute Maximum Ratings Parameter Storage Temperature Operating Temperature Average Input Current Peak Transient Input Current (<1 µs pulse width, 300 pps) Reverse Input Voltage “High” Peak Output Current “Low” Peak Output Current Supply Voltage Input Current (Rise/Fall Time) Output Voltage Output Power Dissipation Total Power Dissipation Lead Solder Temperature Solder Reflow Temperature Profile Recommended Operating Conditions Parameter Power Supply Voltage Input Current (ON) HCPL-3120 HCPL-J312 HCNW3120 Input Voltage (OFF) Operating Temperature 9 ...
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Electrical Specifications (DC) Over recommended operating conditions (T HCNW3120 I = 10 to 16mA, V F(ON) F(OFF) Parameter Symbol Device High Level Output I OH Current Low Level Output I OL Current High Level Output V OH Voltage Low Level Output ...
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Switching Specifications (AC) Over recommended operating conditions (T HCNW3120 I = 10 to 16mA, V F(ON) F(OFF) Parameter Symbol Propagation Delay Time t PLH to High Output Level Propagation Delay Time t PHL to Low Output Level Pulse Width Distortion PWD Propagation Delay PDD Difference Between Any (t - t PHL Two Parts Rise Time t r Fall Time ...
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Package Characteristics Over recommended temperature (T Parameter Symbol Input-Output Momentary V ISO Withstand Voltage** Resistance R I-O (Input-Output) Capacitance C I-O (Input-Output) LED-to-Case Thermal q LC Resistance q LED-to-Detector Thermal ...
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-100 mA OUT -40 - 100 T – TEMPERATURE ...
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HCPL-3120 OUTPUT = OPEN -40 - 100 T – TEMPERATURE – °C A Figure 9. I vs. ...
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I – FORWARD LED CURRENT – Figure 15. Transfer characteristics. HCPL-3120 fig 15 HCPL-3120 1000 T = 25°C A 100 ...
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Figure 18. I Test circuit. OL HCPL-3120 fig 0.1 µ Figure 20. V Test circuit. OL HCPL-3120 fig 20 ...
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500 Ω + – 10 KHz 50% DUTY 3 CYCLE 4 Figure 23 and t test circuit and waveforms. PLH PHL ...
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Applications Information Eliminating Negative IGBT Gate Drive (Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) To keep the IGBT firmly off, the HCPL-3120 has a very low maximum V specification of 0.5 V . The HCPL-3120 OL realizes this very low V by using a DMOS transistor OL with 1 Ω (typical) on resistance in its pull ...
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Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses. (Discussion applies to HCPL-3120, HCPL-J312 and HCNW3120) Step 1: Calculate Rg Minimum from the I tion. The IGBT and Rg in Figure 26 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL- 3120. (V – V - V ) Rg ≥ ——————— ...
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Thermal Model (Discussion applies to HCPL-3120, HCPL- J312 and HCNW3120) The steady state thermal model for the HCPL-3120 is shown in Figure 28. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through q raises the case temperature T accordingly. The value C of q depends on the conditions ...
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θ = 467 °C/W θ = 126 °C θ °C/ Figure 28. Thermal model. LED Drive Circuit Considerations for Ultra High CMR ...
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CMR with the LED On (CMR ). H A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriv- ing the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum I of 5 mA to achieve 25 kV/ FLH µs CMR. CMR with the LED Off (CMR ...
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Under Voltage Lockout Feature. (Discussion applies to HCPL-3120, HCPL-J312, and HCNW3120) The HCPL-3120 contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-3120 supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low re- sistance state. When the HCPL-3120 output is in the high state and the supply voltage drops below the HCPL- 3120 V threshold (9.5 < V UVLO– UVLO– coupler output will go into the low state with a typical ...
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To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case con-ditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 35. The amount of delay necessary to achieve this conditions is equal to the maximum value of the propa- gation delay difference specification, PDD specified to be 350 ns over the operating temperature range of -40°C to 100°C. Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum HCPL-3120 OPTION 060éHCPL-J312 ...