FDCC1602N-FLYYBW-51LK FORDATA, FDCC1602N-FLYYBW-51LK Datasheet - Page 16
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FDCC1602N-FLYYBW-51LK
Manufacturer Part Number
FDCC1602N-FLYYBW-51LK
Description
DISP, LCD, 16X2, EURO, Y/G, BL
Manufacturer
FORDATA
Datasheet
1.FDCC1602N-FLYYBW-51LK.pdf
(22 pages)
Specifications of FDCC1602N-FLYYBW-51LK
No. Of Digits / Alpha
32
Character Count X Line
16 X 2
Character Size
4.35mm
Supply Voltage
5V
Display Area Width
64.5mm
Display Area Height
13.8mm
Operating
RoHS Compliant
Display Mode
Transflective
Backlighting Colour
Yellow Green
Backlighting Color
Yellow Green
I. Read Busy Flag & Address
This instruction shows whether IC is in internal operation or not .
If BF is High, internal operation is in progress and shall wait until BF is to be
Low, which by then the next instruction can be performed. In this instruction
you and also read the value of the address counter.
J. Write data to RAM
Write binary 8-bit data to DDRAM/CGRAM.
The selection of RAM from DDRAM,and CGRAM,is set by the previous address set
instruction(DDRAM address set,CGRAM address set).
RAM set instruction can also determine the AC direction to RAM.
After write operation, the address is automatically increased /decreased by 1,according the
entry mode.
K. Read data from RAM
Read binary 8-bit data from DDRAM/CGRAM.
The selection of RAM is set by the previous address set instruction.If the address set
instruction of RAM is not performed before this instruction, the data that has been read
first is invalid, as the direction of AC is not yet determined. If RAM data is read several
times without RAM address instructions set before read operation,the correct RAM data
can be obtained from the second. But the first data would be incorrect,as there is no time
margin to transfer RAM data.
FORDATA ELECTRONIC CO.,LTD
PROFESSIONAL LCD SUPPLIER FROM CHINA
RS
RS
RS
0
1
1
R/W
R/W
R/W
1
1
0
DB7
DB7
DB7
BF
D7
D7
AC6
DB6
DB6
DB6
D6
D6
BOOKBINDING AREA
AC5
DB5
DB5
DB5
D5
D5
AC4
DB4
DB4
DB4
D4
D4
PRODUCT
SPEC.
AC3
DB3
DB3
DB3
D3
D3
AC2
DB2
DB2
DB2
FDCC1602N-FLYYBW-51LK
D2
D2
MODE NO.
AC1
DB1
DB1
DB1
D1
D1
AC0
DB0
DB0
DB0
D0
D0
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