ST700C12L0L Vishay, ST700C12L0L Datasheet - Page 2

• Manufacturer Part Number: ST700C12L0L
• Description: SILICON CONTROLLED RECTIFIER,1.2kV V(DRM),910A I(T),TO-200AC
• Manufacturer: Vishay

Specifications of ST700C12L0L

• Rated Repetitive Off-state Voltage Vdrm: 1200 V
• Off-state Leakage Current @ Vdrm Idrm: 80 mA
• Holding Current (ih Max): 600 mA
• Mounting Style: SMD/SMT
• Package / Case: TO-200AC
• Breakover Current Ibo Max: 16400 A
• Gate Trigger Current (igt): 200 mA
• Gate Trigger Voltage (vgt): 3 V
• Repetitive Peak Forward Blocking Voltage: 1200 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ST700CLPbF Series
Vishay High Power Products
www.vishay.com
2
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Maximum average on-state current
at heatsink temperature
Maximum RMS on-state current
Maximum peak, one-cycle
non-repetitive surge current
Maximum I
Maximum I
Low level value of threshold voltage
High level value of threshold voltage
Low level value of on-state slope resistance
High level value of on-state slope resistance
Maximum on-state voltage
Maximum holding current
Typical latching current
SWITCHING
PARAMETER
Maximum non-repetitive rate of rise
of turned-on current
Typical delay time
Typical turn-off time
BLOCKING
PARAMETER
Maximum critical rate of rise of
off-state voltage
Maximum peak reverse and
off-state leakage current
2
2
t for fusing
√t for fusing
For technical questions, contact: [e-mail]
SYMBOL
SYMBOL
SYMBOL
(Hockey PUK Version), 910 A
V
V
I
T(RMS)
dV/dt
I
I
dI/dt
I
I
T(TO)1
T(TO)2
V
RRM,
T(AV)
I
DRM
TSM
I
2
r
r
t
t
I
I
2
TM
t1
t2
H
d
q
Phase Control Thyristors
√t
L
t
Gate drive 20 V, 20 Ω, t
T
Gate current 1 A, dI
V
I
V
T
T
180° conduction, half sine wave
double side (single side) cooled
DC at 25 °C heatsink temperature double side cooled
t = 10 ms
t = 8.3 ms
t = 10 ms
t = 8.3 ms
t = 10 ms
t = 8.3 ms
t = 10 ms
t = 8.3 ms
t = 0.1 to 10 ms, no voltage reapplied
(16.7 % x π x I
(I > π x I
(16.7 % x π x I
(I > π x I
I
T
TM
pk
J
J
d
R
J
J
= T
= 0.67 % V
= T
= T
= 25 °C, anode supply 12 V resistive load
= 2000 A, T
= 50 V, dV/dt = 20 V/µs, gate 0 V 100 Ω, t
= 750 A, T
J
J
J
maximum linear to 80 % rated V
maximum, anode voltage ≤ 80 % V
maximum, rated V
T(AV)
T(AV)
), T
), T
DRM
J
No voltage
reapplied
100 % V
reapplied
No voltage
reapplied
100 % V
reapplied
T(AV)
T(AV)
J
= T
J
J
= T
TEST CONDITIONS
TEST CONDITIONS
TEST CONDITIONS
= T
= T
, T
J
< I < π x I
< I < π x I
g
J
J
maximum, dI/dt = 60 A/µs,
/dt = 1 A/µs
J
J
maximum, t
= 25 °C
maximum
maximum
RRM
RRM
r
≤ 1 µs
DRM
T(AV)
T(AV)
Sinusoidal half wave,
initial T
/V
RRM
p
), T
), T
= 10 ms sine pulse
applied
J
J
J
= T
= T
= T
DRM
J
J
J
DRM
maximum
maximum
maximum
p
= 500 µs
Document Number: 94413
910 (355)
VALUES
VALUES
VALUES
Revision: 11-Aug-08
55 (85)
15 700
16 400
13 200
13 800
12 321
1000
1857
1232
1125
1000
1.00
1.13
0.40
0.35
1.80
500
871
795
600
150
1.0
80
UNITS
UNITS
UNITS
kA
kA
A/µs
V/µs
mA
mΩ
mA
µs
°C
A
A
V
V
2
2
√s
s