XC4010E-3PQ160I Xilinx Inc, XC4010E-3PQ160I Datasheet - Page 20

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XC4010E-3PQ160I

Manufacturer Part Number
XC4010E-3PQ160I
Description
IC FPGA I-TEMP 5V 3SPD 160-PQFP - XC4010E-3PQ160I
Manufacturer
Xilinx Inc
Series
XC4000E/Xr
Datasheet

Specifications of XC4010E-3PQ160I

Number Of Logic Elements/cells
950
Number Of Labs/clbs
400
Total Ram Bits
12800
Number Of I /o
129
Number Of Gates
10000
Voltage - Supply
4.5 V ~ 5.5 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
160-BQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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XC4000E and XC4000X Series Field Programmable Gate Arrays
Any XC4000 Series 5-Volt device with its outputs config-
ured in TTL mode can drive the inputs of any typical
3.3-Volt device. (For a detailed discussion of how to inter-
face between 5 V and 3.3 V devices, see the 3V Products
section of The Programmable Logic Data Book .)
Supported destinations for XC4000 Series device outputs
are shown in
An output can be configured as open-drain (open-collector)
by placing an OBUFT symbol in a schematic or HDL code,
then tying the 3-state pin (T) to the output signal, and the
input pin (I) to Ground. (See
Table 12: Supported Destinations for XC4000 Series
Outputs
Output Slew Rate
The slew rate of each output buffer is, by default, reduced,
to minimize power bus transients when switching non-criti-
cal signals. For critical signals, attach a FAST attribute or
property to the output buffer or flip-flop.
For XC4000E devices, maximum total capacitive load for
simultaneous fast mode switching in the same direction is
200 pF for all package pins between each Power/Ground
pin pair. For XC4000X devices, additional internal
6-24
Figure 18: Open-Drain Output
Any typical device, Vcc = 3.3 V,
CMOS-threshold inputs
Any device, Vcc = 5 V,
TTL-threshold inputs
Any device, Vcc = 5 V,
CMOS-threshold inputs
1. Only if destination device has 5-V tolerant inputs
Destination
Table
12.
OBUFT
Product Obsolete or Under Obsolescence
Figure
CMOS
3.3 V,
18.)
Unreliable
XC4000 Series
OPAD
Data
X6702
Outputs
TTL
5 V,
CMOS
some
5 V,
1
Power/Ground pin pairs are connected to special Power
and Ground planes within the packages, to reduce ground
bounce. Therefore, the maximum total capacitive load is
300 pF between each external Power/Ground pin pair.
Maximum loading may vary for the low-voltage devices.
For slew-rate limited outputs this total is two times larger for
each device type: 400 pF for XC4000E devices and 600 pF
for XC4000X devices. This maximum capacitive load
should not be exceeded, as it can result in ground bounce
of greater than 1.5 V amplitude and more than 5 ns dura-
tion. This level of ground bounce may cause undesired
transient behavior on an output, or in the internal logic. This
restriction is common to all high-speed digital ICs, and is
not particular to Xilinx or the XC4000 Series.
XC4000 Series devices have a feature called “Soft
Start-up,” designed to reduce ground bounce when all out-
puts are turned on simultaneously at the end of configura-
tion.
device starts up, the first activation of the outputs is auto-
matically slew-rate limited. Immediately following the initial
activation of the I/O, the slew rate of the individual outputs
is determined by the individual configuration option for each
IOB.
Global Three-State
A separate Global 3-State line (not shown in
Figure
state, unless boundary scan is enabled and is executing an
EXTEST instruction. This global net (GTS) does not com-
pete with other routing resources; it uses a dedicated distri-
bution network.
GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. A specific pin loca-
tion can be assigned to this input using a LOC attribute or
property, just as with any other user-programmable pad. An
inverter can optionally be inserted after the input buffer to
invert the sense of the Global 3-State signal. Using GTS is
similar to GSR. See
Alternatively, GTS can be driven from any internal node.
When the configuration process is finished and the
16) forces all FPGA outputs to the high-impedance
Figure 2 on page 11
May 14, 1999 (Version 1.6)
for details.
Figure 15
or
R

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