SMDA05CN-5.TBT Semtech, SMDA05CN-5.TBT Datasheet - Page 5

• Manufacturer Part Number: SMDA05CN-5.TBT
• Description: TVS DIODE ARRAY, 300W, 5V, SOIC
• Manufacturer: Semtech

Specifications of SMDA05CN-5.TBT

• Reverse Stand-off Voltage Vrwm: 5V
• Breakdown Voltage Range: 6V
• Clamping Voltage Vc Max: 11V
• Diode Configuration: Bidirectional
• Peak Pulse Current Ippm: 20A
• Diode Case Style: SOIC
• No. Of Pins: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Connection for Protection of Four Data Lines
The SMDAxxC series of devices are designed to protect
up to four data lines. The devices are connected as
follows:
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of ESD induced transients. The following guidelines are
recommended:
Matte Tin Lead Finish
Matte tin has become the industry standard lead-free
replacement for SnPb lead finishes. A matte tin finish
is composed of 100% tin solder with large grains.
Since the solder volume on the leads is small com-
pared to the solder paste volume that is placed on the
land pattern of the PCB, the reflow profile will be
determined by the requirements of the solder paste.
Therefore, these devices are compatible with both
lead-free and SnPb assembly techniques. In addition,
unlike other lead-free compositions, matte tin does not
have any added alloys that can cause degradation of
the solder joint.
PROTECTION PRODUCTS
PROTECTION PRODUCTS
Applications Information
2005 Semtech Corp.
The SMDAxxC are bidirectional devices and are
designed for use on lines where the normal operat-
ing voltage is above and below ground. Pins 1, 2,
3, and 4 are connected to the protected lines.
Pins 5, 6, 7, and 8 are connected to ground. Since
the device is electrically symmetrical, these connec-
tions may be reversed. The ground connections
should be made directly to the ground plane for
best results. The path length is kept as short as
possible to reduce the effects of parasitic induc-
tance in the board traces.
Place the TVS near the input terminals or connec-
tors to restrict transient coupling.
Minimize the path length between the TVS and the
protected line.
Minimize all conductive loops including power and
ground loops.
The ESD transient return path to ground should be
kept as short as possible.
Never run critical signals near board edges.
Use ground planes whenever possible.
5
SMDA05C THRU SMDA24C
From Connector
1
2
3
4
1
2
3
4
I/O Line Protection
Typical Connection
Circuit Diagram
To Protected
Device
www.semtech.com
8
7
6
5
8
7
6
5
Ground