LSN2-T/22-D12NG-C Murata Power Solutions Inc, LSN2-T/22-D12NG-C Datasheet - Page 8

• Manufacturer Part Number: LSN2-T/22-D12NG-C
• Description: DC/DC Converter
• Manufacturer: Murata Power Solutions Inc
• Series: LSN2r

Specifications of LSN2-T/22-D12NG-C

• No. Of Outputs: 1
• Input Voltage: 8.3V To 14V
• Power Rating: 112W
• Output Current: 22A
• Approval Bodies: UL, CSA
• Supply Voltage: 14VDC
• Dc / Dc Converter Case Style: SIP
• Dc/dc Converter Mounting: Through Hole
• Product: Non-Isolated / POL
• Output Power: 110 W
• Input Voltage Range: 8.3 V to 14 V
• Input Voltage (nominal): 12 V
• Number Of Outputs: 1
• Output Voltage (channel 1): 0.8 V to 5 V
• Output Current (channel 1): 22 A
• Package / Case Size: SIP
• Output Type: Low Voltage Selectable
• Output Voltage: 0.8 V to 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LSN2 Power Sequencing
Whereas in the old days, one master switch simultaneously turned on the
power for all parts of a system, many modern systems require multiple supply
voltages for different on-board sections. Typically the CPU or microcontroller
needs 1.8 Volts or lower. Memory (particularly DDR) may use 1.8 to 2.5 Volts.
Interface “glue” and “chipset” logic might use +3.3Vdc power while Input/
Output subsystems may need +5V. Finally, peripherals use 5V and/or 12V.
Timing is Everything
This mix of system voltages is being distributed by several local power solu-
tions including Point-of-load (POL) DC/DC converters and sometimes a linear
regulator, all sourced from a master AC power supply. While this mix of volt-
ages is challenging enough, a further diffi culty is the start-up and shutdown
timing relationship between these power sources and relative voltage differ-
ences between them.
For many systems, the CPU and memory must be powered up, boot-strap
loaded and stabilized before the I/O section is turned on. This avoids uncom-
manded data bytes being transferred, compromising an active external
network or placing the I/O section in an undefi ned mode. Or it keeps bad com-
mands out of disk and peripheral controllers until they are ready to go to work.
Another goal for staggered power-up is to avoid an oversize load applied to
the master source all at once. A more serious reason to manage the timing
and voltage differences is to avoid either a latchup condition in program-
mable logic (a latchup might ignore commands or would respond improperly
to them) or a high current startup situation (which may damage on-board
circuits). And on the power down phase, inappropriate timing or voltages can
cause interface logic to send a wrong “epitaph” command.
STARTUP SEQUENCE:
CPU
POL A
POL B
Figure 7. Power Up/Down Sequencing Controller
ENABLE
SEQUENCING
CONTROLLER
“ALL ON”
OFF
OFF
TO OTHER POLs
+12Vdc
Settling
Delay
ON
ENABLE
ENABLE
+V
+V
IN
IN
ON
POL
POL
A
B
+5V
LOADS
+3.3V
LOADS
TIME
www.murata-ps.com
Two Approaches
There are two ways to manage these timing and voltage differences. Either
the power up/down sequence can be controlled by discrete On/Off logic con-
trols for each power supply (see Figure 7). Or the power up/down cycle is set
by Sequencing or Tracking circuits. Some systems combine both methods.
The fi rst system (discrete On/Off controls) applies signals from an already-
powered logic sequencer or dedicated microcontroller which turns on each
downstream power section in cascaded series. This of course assumes all
POL’s have On/Off controls. A distinct advantage of the sequencing controller
is that it can produce an “All On” output signal to state that the full system is
stable and ready to go to work. For additional safety, the sequencer can moni-
tor the output voltages of all downstream POL’s with an A/D converter system.
However the sequencer controller has some obvious diffi culties besides
extra cost, wiring and programming complexity. First, power is applied as a
fast-rising, all-or-nothing step which may be unacceptable to certain circuits,
especially large output bypass capacitors. These could force POL’s into
overcurrent shutdown. And some circuits (such as many linear regulators and
some POL’s) may not have convenient start-up controls. This requires design-
ing and fabricating external power controls such as high-current MOSFET’s.
If the power up/down timing needs to be closely controlled, each POL must be
characterized for start-up and down times. These often vary—one POL may
stabilize in 15 milliseconds whereas another takes 50 milliseconds. Another
problem is that the sequencing controller itself must be “already running” and
stabilized before starting up other circuits. If there is a glitch in the system,
the power up/down sequencer could get out of step with possible disastrous
results. Lastly, changing the timing may require reprogramming the logic
sequencer or rewriting software.
Sequence/Track Input
A different power sequencing solution is employed on DATEL’s LSN2 DC/DC
converter. After external input power is applied and the converter stabilizes,
a high impedance Sequence/Track input pin accepts an external analog volt-
age. The output power voltage will then track this Sequence/Track input at
a one-to-one ratio up to the nominal set point voltage for that converter. This
Sequencing input may be ramped, delayed, stepped or otherwise phased as
needed for the output power, all fully controlled by the user’s simple external
circuits. As a direct input to the converter’s feedback loop, response to the
Sequence/Track input is very fast (milliseconds).
By properly controlling this Sequence pin, most operations of the discrete
On/Off logic sequencer may be duplicated. The Sequence pin system does
not use the converter’s Enable On/Off control (unless it is a master emergency
shut down system).
Power Phasing Architectures
Observe the simplifi ed timing diagrams below. There are many possible power
phasing architectures and these are just some examples to help you analyze
your system. Each application will be different. Multiple output voltages may
require more complex timing than that shown here.
22A Selectable-Output DC/DC Converters
25 Jun 2010
LSN2-T/22-D12
MDC_LSN2-T/22-D12_B03Δ
Non-isolated, DOSA-SIP,
email: [e-mail]
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