83696 SENSONOR TECHNOLOGIES AS, 83696 Datasheet - Page 7

• Manufacturer Part Number: 83696
• Description: SENSOR, PRESSURE, COMP, SP100-15
• Manufacturer: SENSONOR TECHNOLOGIES AS

Specifications of 83696

• Operating Temperature Range: -40°C To +125°C
• Pressure Type: Absolute
• Ic Generic Number: SP100-15
• No. Of Pins: 14
• Operating Pressure Range: 0 To 1500kPa
• Sensor Case Style: SOIC
• Supply Voltage: RoHS Compliant
• Rohs Compliant: Yes

5
6
The product provides two outputs, which may be used to interrupt or reset a microcontroller. Each output provides a
pulse at regular intervals. The “wake-up and reset” are active low outputs. The Wake Up period is programmable
from 1 to 256 seconds, in 1 second intervals. The command to set this is found in the table of chapter 6.2.
Table 5.1 Wake-up and reset outputs
Notes:
The SPI interface is the communication protocol to the external microcontroller. This maximum serial clock frequency
is 500 kHz.
The SPI consists of a shift register, a command latch and failure latches, and encoder/decoder logic.
6.1
TS1482 rev. 2
Interval timing drift over supply voltage
Interval timing drift over temperature
When NCS is high, any signals at the SCLK and SDI pins are ignored, and SDO is forced into a high impedance
state.
During the NCS high-to-low transition, the SPI response word is multiplexed from the latch(es) that was(were)
defined by the last command present in the shift register. The SCLK pin must be low when NCS goes low.
At each clock rising edge after NCS has gone low, the response word is serially shifted out of the ASIC at the
SDO pin, LSB first. At each clock falling edge after NCS has gone low, the new control word is serially shifted into
the ASIC at the SDI pin, LSB first.
The command bits of the received SPI word are then decoded to determine the destination address for the data
bits. After the 8
stored in the ASIC SPI shift register to be transferred into the latch which address was decoded from the SPI shift
register command bits.
If the number of clock pulses before NCS goes high is different from 0, 8 or 16, a digital filter prevents execution of
the received command. Also to notice; A valid NCS pulse with 0 clock pulses will cause the previous command to
be executed again.
A Failure Status Indicator (FSI) is a logical OR of all bits in the status register, except for bit 6. However, for
SP100-15 the FSI indication should be ignored.
To validate P, T and V measurements for SP100-15 the Status register should be checked. This is done by
executing the RSR command after each measurement and evaluating the content. The corresponding
measurement result should be rejected if, and only if, the status register indicates an error. Status bits of interest
for measurement validity are all except bit 5 and 6 (see more in chapter 6.4).
Wake-Up and Reset Outputs
Serial Interface
1)
The product has two oscillators: One low-power oscillator, which runs at about 2.5 kHz and is used for interval timing, and a 2 MHz
SPI Protocol
oscillator used for measurements and data transmission. Due to its very low current consumption, the low-power oscillator is sensitive to
temperature and supply voltage variation. To keep the interval lengths constant under different conditions, the low-power oscillator is
compared to the 2 MHz oscillator during each measurement, and a correction is applied to the interval count. This operation is called an
auto calibration. The stability of the interval depends on the change in temperature or supply voltage since the last measurement.
Wake Up Width
Reset period
Reset width
Parameter
th
clock falling edge has occurred, the following NCS low-to-high transition causes the data bits
1)
1)
0.13
0.13
Min
- 7 -
Typ
-15
0.6
51
Max
-40
2.5
2.5
1
%/°C
Unit
%/V
min
ms
ms