MCZ33905BS5EK Freescale Semiconductor, MCZ33905BS5EK Datasheet - Page 42
MCZ33905BS5EK
Manufacturer Part Number
MCZ33905BS5EK
Description
IC SBC CAN HS 5.0V 32SOIC
Manufacturer
Freescale Semiconductor
Datasheet
1.MCZ33904A5EKR2.pdf
(98 pages)
Specifications of MCZ33905BS5EK
Applications
System Basis Chip
Interface
CAN, LIN
Voltage - Supply
5.5 V ~ 27 V
Package / Case
*
Mounting Type
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCZ33905BS5EK
Manufacturer:
FREESCALE
Quantity:
20 000
Principle
mode (LP V
mode, the device will generate a periodic INT pulse.
acknowledge the INT by sending SPI commands before the
end of the next INT period in order to keep the process going.
remains in LP V
are issued properly. When no/improper SPI commands are
sent, the device will cease Cyclic INT operation and leave LP
V
into Normal Request mode.
similar as in LP V
Operation
cyclic Interrupt period (SPI command without parity bit)].
Mode.
42
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FUNCTIONAL DEVICE OPERATION
CYCLIC INT OPERATION DURING LOW POWER VDD ON MODE
Prepare Low Power V
DD
This function can be used only in Low Power V
When Cyclic INT is selected and device is in LP V
Upon reception of the INT pulse, the MCU must
When Cyclic INT is selected and operating, the device
VDD current capability and VDD regulator behavior is
Cyclic INT period selection: register timer B
SPI command in hex 0x56xx [example; 0x560E for 512ms
This command must be send while the device is in Normal
ON mode by issuing a reset. The device will then enter
with Cyclic INT
SPI
INT
Timer B
NORMAL MODE
Legend for SPI commands
DD
ON).
Write Timer B, select Cyclic INT period (ex: 512 ms, 0x560E)
Write Device mode: LP V
Read RNDM code
Write RNDM code inv.
SPI wake up: 0x5C10
ON mode
DD
LP V
DD
DD
ON mode, assuming the SPI commands
DD
ON mode.
ON
Cyclic INT period
CYCLIC INT OPERATION DURING LOW POWER VDD ON MODE
1st period
DD
ON with Cyclic INT enable (example: 0x5C90)
In Low Power V
Cyclic INT period
2nd period
Figure 24. Cyclic Interrupt Operation
DD
DD
LP V
ON with Cyclic INT
DD
ON
DD
ON
Cyclic INT period
ON MODE
3rd period
using the following command: MOSI 0x1B00 device report on
MISO second byte the RNDM code (MISO bit 0-7).
inverted: 0x5A RNDb.
set in LP V
command is necessary until the first INT pulse occurs. The
acknowledge process must start only after the 1st INT pulse.
wake-up from LP V
enter into Normal Request mode.
device is in LP V
device will cease Cyclic INT operation and leave LP V
mode by issuing a reset. The device will then enter into
Normal Request mode.
Cyclic Interrupt operation.
SPI commands to acknowledge INT: (2 commands)
- read the Random code via the W/D register address
- write W/D refresh command using the random code
These commands can occur at any time within the period.
Initial entry in LP mode with Cyclic INT: after the device is
Leave Low Power Mode with Cyclic INT:
This is done by a SPI wake-up command, similar to SPI
Improper SPI command while Cyclic INT operates:
When no/improper SPI commands are sent, while the
The figure below
Leave LP V
DD
ON mode, with cyclic INT enable, no SPI
DD
DD
ON and Cyclic INT due to improper operation
LP V
SPI
RST
INT
DD
ON mode with Cyclic INT enable, the
(Figure
DD
ON mode: 0x5C10. The device will
Analog Integrated Circuit Device Data
acknowledge SPI command
ON MODE
Cyclic INT period
Cyclic INT period
24) describes the complete
Leave Low Power
Improper or no
V
DD
Freescale Semiconductor
ON mode
MODE
NORMAL
REQUEST
RESET and
NORMAL
REQUEST
MODE
DD
ON