DS1822Z Maxim Integrated Products, DS1822Z Datasheet - Page 9
![IC THERMOMETER ECONO DIG 8-SOIC](/photos/19/51/195174/8-soic_sml.jpg)
DS1822Z
Manufacturer Part Number
DS1822Z
Description
IC THERMOMETER ECONO DIG 8-SOIC
Manufacturer
Maxim Integrated Products
Datasheet
1.DS1822Z.pdf
(21 pages)
Specifications of DS1822Z
Sensing Temperature
-55°C ~ 125°C
Output Type
Digital
Voltage - Supply
3 V ~ 5 V
Accuracy
±2°C
Package / Case
8-SOIC (0.154", 3.90mm Width)
Full Temp Accuracy
+/- 3 C
Digital Output - Bus Interface
Serial (1-Wire)
Digital Output - Number Of Bits
12 bit
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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is available in Application Note 27 entitled Understanding and Using Cyclic Redundancy Checks with
Dallas Semiconductor Touch Memory Products.
CRC GENERATOR Figure 9
1-WIRE BUS SYSTEM
The 1-Wire bus system uses a single bus master to control one or more slave devices. The DS1822 is
always a slave. When there is only one slave on the bus, the system is referred to as a “single-drop”
system; the system is “multidrop” if there are multiple slaves on the bus.
All data and commands are transmitted least significant bit first over the 1-Wire bus.
The following discussion of the 1-Wire bus system is broken down into three topics: hardware
configuration, transaction sequence, and 1-Wire signaling (signal types and timing).
HARDWARE CONFIGURATION
The 1-Wire bus has by definition only a single data line. Each device (master or slave) interfaces to the
data line via an open drain or 3-state port. This allows each device to “release” the data line when the
device is not transmitting data so the bus is available for use by another device. The 1-Wire port of the
DS1822 (the DQ pin) is open drain with an internal circuit equivalent to that shown in Figure 10.
The 1-Wire bus requires an external pullup resistor of approximately 5 kΩ; thus, the idle state for the 1-
Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle
state if the transaction is to resume. Infinite recovery time can occur between bits so long as the 1-Wire
bus is in the inactive (high) state during the recovery period. If the bus is held low for more than 480μs,
all components on the bus will be reset.
HARDWARE CONFIGURATION Figure 10
(MSB)
T
R
X
X
V
PU
4.7k
R
T
X
X
XOR
= TRANSMIT
= RECEIVE
1-wire Bus
9 of 21
XOR
DQ
Pin
Typ.
5μA
DS1822 1-WIRE PORT
(LSB)
MOSFET
100Ω
T
R
X
X
INPUT
XOR
DS1822