ISL76683AROZ-T7 Intersil, ISL76683AROZ-T7 Datasheet - Page 12

• Manufacturer Part Number: ISL76683AROZ-T7
• Description: DIGITAL LIGHT SENSOR ADC 6ODFN
• Manufacturer: Intersil

Specifications of ISL76683AROZ-T7

• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

INTEGRATION TIME IN EXTERNAL TIMING MODE
This timing mode is programmed in the command register
00(hex) bit 5. External Timing Mode is recommended when
integration time can be synchronized to an external signal (such
as a PWM) to eliminate noise.
For Mode1 or Mode2 operation, the integration starts when the
sync_iic command is sent over the I
two sync_iic commands to complete a photodiode conversion.
The integration then stops when another sync_iic command is
received. Writing a logic 1 to the sync_iic bit ends the current
ADC integration and starts another one.
For Mode3, the operation is a sequential Mode1 and Mode2. The
device needs three sync_iic commands to complete two
photodiode measurements. The 1st sync_iic command starts the
conversion of the Diode1. The 2nd sync_iic completes the
conversion of Diode1 and starts the conversion of Diode2. The 3rd
sync_iic pulse ends the conversion of Diode2 and starts over again
to commence conversion of Diode1.
The integration time, t
i
f
The internal oscillator, f
internal and external timing modes, with the same dependence
on R
cycles per integration is no longer fixed at 2
clock cycles varies with the chosen integration time, and is
limited to 2
the integration time must be short enough not to allow an
overflow in the counter register.
t
f
Range1 or Range2.
f
Range3 or Range4.
Noise Rejection
In general, integrating type ADC’s have excellent noise-rejection
characteristics for periodic noise sources whose frequency is an
integer multiple of the integration time. For instance, a 60Hz AC
unwanted signal’s sum from 0ms to k*16.66ms (k = 1,2...k
zero. Similarly, setting the device’s integration time to be an
integer multiple of the periodic noise signal greatly improves the
light sensor output signal in the presence of noise.
DESIGN EXAMPLE 1
The ISL76683 will be designed in a portable system. The
ambient light conditions that the device will be exposed to is at
most 500 lux, which is a good office lighting. The light source has
a 50/60Hz power line noise, which is not visible by the human
eye. The I
t
I
I
int
OSC
OSC
int
2
2
C
C
<
=
is the number of I
is the I
EXT
= 327kHz*100kΩ/R
= 655kHz*100kΩ/R
65,535
------------------ -
f
i
--------- -
f
I 2 C
I 2 C
OSC
. However, in External Timing Mode, the number of clock
2
C clock is 10kHz.
2
16
C operating frequency.
= 65,536. In order to avoid erroneous lux readings,
2
int
C clock cycles to obtain the t
OSC
, is determined by Equation 12:
EXT
EXT
, operates identically in both the
. When Range/Gain is set to
. When Range/Gain is set to
12
2
C lines. The device needs
n
. The number of
int.
(EQ. 12)
(EQ. 13)
ISL76683
i
) is
Solution 1
Using Internal Timing Mode
In order to achieve both 60Hz and 50Hz AC noise rejection, the
integration time needs to be adjusted to coincide with an integer
multiple of the AC noise cycle times.
The first instance of integer values at which t
and 50Hz is when i = 6, and j = 5.
Next, the Gain/Range needs to be determined. Based on the
application condition given, lux(max) = 500 lux, a range of 1000
lux is desirable. This corresponds to a Gain/Range Range1
mode. Also impose a resolution of n = 16-bit. Hence, we choose
Equation 10 to determine R
R
R
The Full Scale Range, FSR, needs to be determined from
Equation 3:
The effective transfer function becomes:
Solution 2
Using External Timing Mode
From Solution 1, the desired integration time is 100ms. Note
that the R
frequency when using external timing mode. Instead, the
integration time is the time between two sync_iic commands
sent through the I
clock cycles to wait between two external timing commands.
i
FSR
FSR
t
t
t
E
I
int
int
int
2
EXT
EXT
C
=
TABLE 14. SOLUTION1 SUMMARY TO EXAMPLE DESIGN PROBLEM
for Internal Timing Mode and Gain/Range is set to Range3 or Range4 only
DESIGN PARAMETER
=
=
=
= f
Gain/Range Mode
data
------------ -
Transfer Function
=
=
2
# of clock cycles
=
i 1 60Hz
6 1 60Hz
=
100ms
(
16
I
(
1000 lux
2000 lux
2
t
------------------------------------------------------------- -
50kΩ
int
C*
⁄
⁄
×
EXT
R
FSR
t
t
×
2000 lux
EXT
int
int
327kHz 100
resistor only determines the inter oscillator
= number of I
)
)
=
100kΩ
------------------ -
=
50kΩ
2
2
j 1 50Hz
(
5 1 50Hz
n
C. The programmer determines how many I
(
×
⁄
⁄
kΩ
)
EXT
2
)
C clock cycles
.
E
Range1 = 1000 lux
=
DATA
-------------- -
2
16
2000 lux
100ms
VALUE
50kΩ
2
int
16
×
2000 lux
rejects both 60Hz
March 17, 2011
FN7697.2
(EQ. 14)
(EQ. 15)
(EQ. 16)
(EQ. 18)
(EQ. 17)
2
C