ISL29011IROZ-T7 Intersil, ISL29011IROZ-T7 Datasheet - Page 5

• Manufacturer Part Number: ISL29011IROZ-T7
• Description: IC PROXIMITY SENSOR AMB LT 8ODFN
• Manufacturer: Intersil

Specifications of ISL29011IROZ-T7

• Output Type: Digital - I²C
• Sensor Type: Light and Proximity
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL29011IROZ-T7TR

Electrical Specifications
NOTES:
PARAMETER
I
I
SUP (IRLED1)
SUP (IRLED2)
5. V
6. 550nm green LED is used in production test. The 550nm LED irradiance is calibrated to produce the same DATA count against an illuminance level
7. 850nm infrared LED is used in production test. The 850nm LED irradiance is calibrated to produce the same DATA_IR count against an illuminance
8. See “Register Set” on page 8.
I2C Electrical Specifications
Duty Cycle
PARAMETER
PROX-IR
f
f
V
IRLED1
IRLED2
of 300 lux fluorescent light.
level of 210 lux sunlight at sea level.
PROX
IRLED
t
SUP
t
t
t
HD:STA
HD:DAT
SU:DAT
SU:STA
t
t
t
t
V
r
f
V
f
HIGH
V
LOW
SCL
V
t
t
V
SP
AA
C
t
hys
t
I
OL
I
R
IH
F
2
IL
i
i
is the common voltage to V
C
Voltage Head Room of IRDR Pin
Rise Time for IRDR Source Current
Fall Time for IRDR Source Current
IR LED Modulation Frequency
IR LED Modulation Frequency
Supply Current of Proximity Sensing
Supply Current of Proximity Sensing
Duty Cycle of IR LED Modulation
Differential ADC Output of IR and
Proximity Sensing With Object Far
Away to Provide No Reflection
Supply Voltage Range for I
SCL Clock Frequency
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
Hysteresis of Schmitt Trigger Input
Low-level output voltage (open-drain) at 4mA sink
current
Input Leakage for each SDA, SCL pin
Pulse width of spikes that must be suppressed by
the input filter
SCL Falling Edge to SDA Output Data Valid
Capacitance for each SDA and SCL pin
Hold Time (Repeated) START Condition
LOW Period of the SCL clock
HIGH period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-up Time
Rise Time of both SDA and SCL Signals
Fall Time of both SDA and SCL Signals
DESCRIPTION
5
V
(Continued)
DESCRIPTION
SUP(V
DDD
and V
For SCL and SDA unless otherwise noted, V
16-bit ADC operation (Note 9).
DDD
,V
2
C Interface
DDA
DDA.
)
= 3V, T
R
R
Freq = 0 (Note 8)
Freq = 1 (Note 8)
IS<1:0> = 0, Freq = 0 (Note 8)
IS<1:0> = 0, Freq = 1 (Note 8)
IR and proximity sensing with Range 2 and Scheme 0;
15Ω @ IRDR pin, IS<1:0> = 0, Freq = 0; E = 210 lux,
Sunlight.
LOAD
LOAD
A
= +25°C, R
= 15Ω at IRDR pin, 20% to 80%
= 15Ω at IRDR pin, 80% to 20%
ISL29011
EXT
After this period, the first clock pulse is
generated.
Measured at the 30% of VDD crossing.
= 499kΩ 1% tolerance, 16-bit ADC operation, unless otherwise specified.
CONDITION
CONDITION
SUP(V
DDD
,V
DDA
)
= 3V, T
A
= +25°C, R
20 + 0.1xC
20 + 0.1xC
MIN
0.05V
1300
1.25
MIN
600
600
600
100
1.7
-10
30
EXT
DD
V
= 499kΩ 1% tolerance,
DD
b
b
TYP
360
101
DC
1.0
35
10
51
50
TYP MAX UNIT
- 0.6
February 4, 2010
MAX
3.63
0.55
400
900
0.4
10
50
10
FN6467.3
kHz
UNIT
µA
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
kHz
V
V
V
V
V
mA
mA
ns
ns
%
%
V