MX868RTR IXYS, MX868RTR Datasheet - Page 4

• Manufacturer Part Number: MX868RTR
• Description: IC FLUX SENSOR 12BIT DGTL 8-DFN
• Manufacturer: IXYS
• Type: Special Purposer

Specifications of MX868RTR

• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 3mA
• Output Type: Digital, 12-Bit Serial
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VFDFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Sensing Range: -
• Current - Output (max): -
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MX868
The MX868 contains a power-on reset circuit that resets all the internal flip-flops and initializes the
internal registers to zero. The MX868 will reset if the voltage at terminal PWR drops below 3.2 V to 3.8 V.
SYNCHRONOUS SERIAL I/O
The MX868 (slave) can communicate with a microcomputer (master) via a three wire plus chip select
serial interface. Chip select CS*, serial clock SCK, and serial data input SDI are output from the master
controller to the MX868.
Serial data output SDO is driven by the MX868 when selected by CS* = 0.
SDO is high impedance when CS* = 1.
SCK and SDI are don't care when CS* = 1.
SDI is captured by the rising edge of SCK.
SDO changes in response to the falling edge of SCK.
Read 12-bit data D[11:0] when SDI = logic 0
Write command timing: (Bit Field A[2:0] , B[5:0], OTP Bit Zp)
The exponentially weighted moving average digital filter has a transfer function equivalent to a first order
low pass filter.
The I/O timing remains exactly the same when the filter is used. No decimation is performed.
Let T = Sample interval (the time from CS* falling edge to CS* falling edge). Then bandwidth = 1/(2*pi*T).
Also if W = Sample weighting, then the digital output = W*(current sample) + (1-W)*(previous value).
At power-on the previous value is initialized to zero. A programmed change in A[2:0] does not reset the
previous value. Therefore when using the filter, multiple samples must be taken at power-on or after
changing A[2:0] before the filtered output will be correct.
MX868
Drawing No. 086809
POWER-ON RESET
SDO
SCK
SDI
SCK
CS*
SDI
CS*
1
The write command SDI input bit pattern is internally latched at the rising edge of
CS* and takes effect at the end of the next A/D conversion following CS* rising.
200 nS min
0
A2
20 nS min
A1
D11
A0
D10 D9
B5
B4
D8
4
B3
D7
B2
D6
60 nS max
B1
D5
B0
D4
D3
D2
D1
IXYS
www.claremicronix.com
D0
Zp
03/03/08