TP3465V National Semiconductor, TP3465V Datasheet - Page 5

• Manufacturer Part Number: TP3465V
• Description: IC,Peripheral Interface,CMOS,LDCC,28PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of TP3465V

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Functional Description
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
PD Pin Definition Register W Register
RESET condition is FFhex (all pins as Inputs)
pd0–7 bits configure the CS0–7 pins as inputs or outputs
For example pd0
0 sets CS0 pin as an output Upon chip RESET the pd0–7
bits are set to 1
SKP MICROWIRE Clock (SK) Polarity W Register
RESET condition is 00hex (Normal MICROWIRE clock)
skp 0 –7 bits set the polarity of the SK MICROWIRE clock
when communicating with device connected to each of the
pins CS0–7 For example skp0
mode (i e SO data output on negative edge of SK clock)
when sending data to device controlled by CS0 pin skp1
1 NSC COMBO II clock format for device controlled by CS1
(i e SO data output on the positive edge of SK clock)
skp7
Bit7
Bit7
pd7
skp6
Bit6
Bit6
pd6
Register
SMB
FMB
FMBD0
FMBD1
FMBD2
FMBD3
FMBD4
FMBD5
FMBD6
FMBD7
CS
SKP
MWM
SKR
ST
PD
skp5
Bit5
Bit5
pd5
e
div2
0
0
0
0
1
1
1
1
1 sets the CS0 pin as an input pd0
skp4
Bit4
Bit4
pd4
div1
0
0
1
1
0
0
1
1
uwdone
mwm7
skp3
Bit3
Bit3
inten
pd3
skp7
Bit7
cs7
pd7
d7
d7
d7
d7
d7
d7
d7
d7
d7
d7
e
div0
0 normal MICROWIRE
0
1
0
1
0
1
0
1
skp2
(Continued)
Bit2
Bit2
pd2
SK
SK
SK
SK
SK
SK
SK
SK
TABLE I Control and Data Registers
mwm6
skp6
Bit6
pd6
cs6
soi
skp1
SK Ratio
e
e
e
e
e
e
e
e
d6
d6
d6
d6
d6
d6
d6
d6
d6
d6
TABLE 2 SK Clock Rate Control
Bit1
Bit1
pd1
0
CKIN
CKIN 2
CKIN 4
CKIN 8
CKIN 16
CKIN 32
CKIN 64
CKIN 128
skp0
Bit0
Bit0
pd0
mwm5
e
e
skp5
Bit5
pd5
cs5
ms
d5
d5
d5
d5
d5
d5
d5
d5
d5
d5
0
e g CKIN
SK
SK
5
e
e
e
e
e
e
e
e
MWM MICROWIRE Mode Register W Register
RESET condition is 00hex
mwm0– 7 bits specify whether 8 or 16 clocks are generated
for devices connected to CS0– 7 pins For example mwm1
CS1 (16 data bits will be shifted out and 16 data bits will be
strobed in) mwm0
vice controlled by CS0 (8 data bits will be shifted out and
strobed in)
SKR MICROWIRE Clock (SK) Rate Register
W Register
The 3 bits div0– 2 give the divide-by value for deriving the
SK clock output rate from the CKIN The maximum CKIN
rate is 20 MHz and the slowest MICROWIRE peripheral
works at 256 kHz Table 2 below gives the division ratios
and some examples
e
mwm7 mwm6 mwm5 mwm4 mwm3 mwm2 mwm1 mwm0
Bit7
inten
5 MHz
2 5 MHz
1 25 MHz
625 kHz
312 5 kHz
156 25 kHz
78 125 kHz
39 06 kHz
Bit7
mwm4
skp4
1 16 clocks will be generated for device controlled by
Bit4
cs4
pd4
d4
d4
d4
d4
d4
d4
d4
d4
d4
d4
0
0
e
Bit6
5 MHz
Bit6
soi
mwm3
skp3
Bit3
cs3
pd3
Bit5
d3
d3
d3
d3
d3
d3
d3
d3
d3
d3
Bit5
ms
0
0
e g CKIN
SK
e
e
e
e
e
e
e
0 8 clocks will be generated for de-
Bit4
Bit4
5 MHz
2 5 MHz
1 25 MHz
625 kHz
312 5 kHz
156 25 kHz
0
mwm2
skp2
Bit2
div2
pd2
cs2
d2
d2
d2
d2
d2
d2
d2
d2
d2
d2
e
0
Bit3
Bit3
20 MHz
0
Bit2
Bit2
div2
mwm1
skp1
Bit1
div1
pd1
cs1
d1
d1
d1
d1
d1
d1
d1
d1
d1
d1
0
Bit1
Bit1
div1
mwm0
skp0
Bit0
Bit0
div0
Bit0
div0
pd0
cs0
d0
d0
d0
d0
d0
d0
d0
d0
d0
d0
0