PIC24FJ96GA008-I/PT Microchip Technology, PIC24FJ96GA008-I/PT Datasheet - Page 7
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PIC24FJ96GA008-I/PT
Manufacturer Part Number
PIC24FJ96GA008-I/PT
Description
IC,MICROCONTROLLER,16-BIT,PIC CPU,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ64GA006-IPT.pdf
(240 pages)
3.PIC24FJ64GA006-IPT.pdf
(22 pages)
Specifications of PIC24FJ96GA008-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
69
Program Memory Size
96KB (32K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
69
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011, DV164033, AC164127, MA240011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUDV164033 - KIT START EXPLORER 16 MPLAB ICD2MA160011 - DAUGHTER BOARD PICDEM LCD 16F91XDM240001 - BOARD DEMO PIC24/DSPIC33/PIC32AC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ96GA008-I/PT
Manufacturer:
Maxim
Quantity:
164
Company:
Part Number:
PIC24FJ96GA008-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC24FJ96GA008-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
10. Module: UART
11. Module: SPI (Master Mode)
© 2009 Microchip Technology Inc.
The Receive Buffer Overrun Error Status bit,
OERR (UxSTA<1>), may set before the UART
FIFO has overflowed. After the fourth byte is
received by the UART, the FIFO is full. The OERR
bit should set after the fifth byte has been received
in the UART Shift register. Instead, the OERR bit
may set after the fourth received byte with the
UART Shift register empty.
Work around
After four bytes have been received by the UART,
the UART Receiver Interrupt Flag bit, U1RXIF
(IFS0<11>) or U2RXIF (IFS1<14>), will be set,
indicating the UART FIFO is full. The OERR bit
may also be set. After reading the UART Receive
Buffer, UxRXREG, four times to clear the FIFO,
clear both the OERR and UxRXIF bits in software.
Affected Silicon Revisions
Master mode receptions using the SPI1 and SPI2
modules may not function correctly for bit rates
above 8 Mbps if the master has the SMP bit
(SPIxCON1<9>) cleared (master samples data at
the middle of the serial clock period).
In this case, the data transmitted by the slave is
received, shifted right by one bit, by the master.
For example, if the data transmitted by the slave
was 0xAAAA, the data received by the master
would be 0x5555 (0xAAAA shifted right by one bit).
Work around
Users may set up the SPI module so that the bit
rate is 8 Mbps or lower.
Alternatively, the bit rate can be configured higher
than 8 Mbps, but the SMP bit (SPIxCON1<9>) of
the SPI master must be set (master samples data
at the end of the serial clock period).
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
A4
A4
X
C1
C1
C2
C2
PIC24FJ128GA010 FAMILY
12. Module: CPU
13 Module: PMP
A DISI instruction may be ignored if the command
is executed in the same instruction cycle as when
the DISICNT register decrements to zero. For
example, if a DISI #5 instruction is performed, the
DISICNT will decrement to zero in six instruction
cycles (5 instruction cycles for the DISI command
plus 1 for the instruction execution). If a second
DISI command executes in the same instruction
cycle that DISCNT reaches zero, the second DISI
instruction will be ignored. In any other instruction
cycle, the second DISI command will perform as
described in the product data sheet.
Work around
To disable interrupts using the DISI instruction,
execute the instruction twice. For example, to
disable interrupts for five instruction cycles, use
the following:
DISI #2 (can be any value except 0)
DISI #5 (number of instruction cycles DISI
This work around ensures a DISI command is not
executed in the same instruction cycle as when the
DISICNT register decrements to zero.
Affected Silicon Revisions
In Master mode (MODE<1:0> = 11 or 10),
back-to-back operations may cause the PMRD
signal to not be generated. This limitation occurs
when the peripheral is configured for zero Wait
states (WAITM<3:0> = 0000).
Work around
The PMRD signal will be generated correctly if a
minimum of one instruction cycle delay is inserted
between the back-to-back operations. A NOP
instruction, or any other instruction, is adequate.
Selecting a delay other than zero will also permit
the PMRD signal to be generated.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
X
will be active)
A4
A4
X
C1
C1
C2
C2
DS80471A-page 7