PIC18LF6720T-I/PT Microchip Technology, PIC18LF6720T-I/PT Datasheet - Page 197
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18LF6720T-I/PT
Manufacturer Part Number
PIC18LF6720T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F8520T-IPT.pdf
(380 pages)
3.PIC18F8520T-IPT.pdf
(40 pages)
4.PIC18F6620-IPT.pdf
(14 pages)
5.PIC18F6620-IPT.pdf
(12 pages)
Specifications of PIC18LF6720T-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
52
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.75K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3840 B
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
52
Number Of Timers
2 x 8 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
Minimum Operating Temperature
- 40 C
On-chip Adc
12 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6720T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F8520T-IPT PDF datasheet #2
- PIC18F8520T-IPT PDF datasheet #3
- PIC18F6620-IPT PDF datasheet #4
- PIC18F6620-IPT PDF datasheet #5
- Current page: 197 of 380
- Download datasheet (7Mb)
17.4.17.3
Bus collision occurs during a Stop condition if:
a)
b)
FIGURE 17-31:
FIGURE 17-32:
2004 Microchip Technology Inc.
After the SDA pin has been deasserted and
allowed to float high, SDA is sampled low after
the BRG has timed out.
After the SCL pin is deasserted, SCL is sampled
low before SDA goes high.
SDA
SCL
PEN
BCLIF
P
SSPIF
SSPIF
BCLIF
SDA
PEN
SCL
Bus Collision During a Stop
Condition
P
PIC18F6520/8520/6620/8620/6720/8720
BUS COLLISION DURING A STOP CONDITION (CASE 1)
BUS COLLISION DURING A STOP CONDITION (CASE 2)
Assert SDA
T
SDA asserted low
BRG
T
BRG
T
BRG
T
BRG
The Stop condition begins with SDA asserted low.
When SDA is sampled low, the SCL pin is allowed to
float. When the pin is sampled high (clock arbitration),
the Baud Rate Generator is loaded with SSPADD<6:0>
and counts down to ‘0’. After the BRG times out, SDA
is sampled. If SDA is sampled low, a bus collision has
occurred. This is due to another master attempting to
drive a data ‘0’ (Figure 17-31). If the SCL pin is
sampled low before SDA is allowed to float high, a bus
collision occurs. This is another case of another master
attempting to drive a data ‘0’ (Figure 17-32).
SCL goes low before SDA goes high,
set BCLIF
T
BRG
T
BRG
‘0’
‘0’
DS39609B-page 195
SDA sampled
low after T
set BCLIF
‘0’
‘0’
BRG
,
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