PIC18LF4580-I/ML Microchip Technology, PIC18LF4580-I/ML Datasheet - Page 150

• Manufacturer Part Number: PIC18LF4580-I/ML
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LLCC,44PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4580-I/ML

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• A/d Bit Size: 10 bit
• A/d Channels Available: 11
• Height: 0.88 mm
• Length: 8 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 8 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2480/2580/4480/4580
FIGURE 11-3:
FIGURE 11-4:
TABLE 11-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT
DS39637D-page 150
PORTD
LATD
TRISD
PORTE
LATE
TRISE
INTCON
PIR1
PIE1
IPR1
ADCON1
CMCON
Legend:
Note 1:
Name
PORTD<7:0>
PORTD<7:0>
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PSPIF
PSPIF
— = unimplemented, read as ‘0’. Shaded cells are not used by the Parallel Slave Port.
These registers are available on PIC18F4X80 devices only.
LATD Output Latch Register
PORTD Data Direction Register
GIE/GIEH
OBF
OBF
CS
WR
RD
IBF
CS
WR
RD
C2OUT
IBF
PSPIE
PSPIP
PSPIF
Bit 7
RD7
IBF
—
—
—
PARALLEL SLAVE PORT WRITE WAVEFORMS
PARALLEL SLAVE PORT READ WAVEFORMS
Q1
PEIE/GIEL
Q1
C1OUT
ADIF
ADIE
ADIP
Bit 6
RD6
OBF
—
—
—
Q2
Q2
TMR0IE
VCFG1
C2INV
IBOV
RCIF
RCIE
RCIP
Bit 5
RD5
Q3
Q3
—
—
Q4
Q4
PSPMODE
VCFG0
INT0IE
C1INV
TXIE
TXIP
Bit 4
TXIF
RD4
—
—
Q1
Q1
PCFG3
Q2
Q2
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
RD3
RE3
CIS
—
—
Q3
Q3
LATE Output Latch Register
TMR0IF
CCP1IE
CCP1IP
TRISE2
CCP1IF
PCFG2
Bit 2
CM2
RD2
RE2
Q4
Q4
TMR2IE
TMR2IP
TRISE1
TMR2IF
PCFG1
Q1
INT0IF
Q1
© 2009 Microchip Technology Inc.
Bit 1
CM1
RD1
RE1
Q2
Q2
TMR1IE
TMR1IP
TRISE0
TMR1IF
PCFG0
RBIF
Bit 0
CM0
RD0
RE0
Q3
Q3
on Page:
Values
Q4
Reset
Q4
58
58
58
58
58
58
55
58
58
58
56
57