PIC18LF4420-I/P Microchip Technology, PIC18LF4420-I/P Datasheet - Page 11
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PIC18LF4420-I/P
Manufacturer Part Number
PIC18LF4420-I/P
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,40PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2420-IML.pdf
(412 pages)
3.PIC18F2420-IML.pdf
(16 pages)
4.PIC18F2420-IML.pdf
(8 pages)
5.PIC18F2420-IML.pdf
(6 pages)
6.PIC18F2420-IML.pdf
(8 pages)
7.PIC18F2420-IML.pdf
(4 pages)
Specifications of PIC18LF4420-I/P
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
MSSP, SPI, I2C, PSP, USART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4420-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
34. Module: EUSART
35. Module: EUSART
36. Module: EUSART
© 2008 Microchip Technology Inc.
Note:
In 9-Bit Asynchronous Full-Duplex Receive mode,
the received data may be corrupted if the TX9D bit
(TXSTA<0>) is not modified immediately after the
RCIDL bit (BAUDCON<6>) is set.
Work around
Write to TX9D only when a reception is not in
progress (RCIDL = 1). Since there is no interrupt
associated with RCIDL, it must be polled in
software to determine when TX9D can be
updated.
Date Codes that pertain to this issue:
All engineering and production devices.
After the last received byte has been read from the
EUSART receive buffer, RCREG, the value is no
longer valid for subsequent read operations.
Work around
The RCREG register should only be read once for
each byte received. After each byte is received
from the EUSART, store the byte into a user vari-
able. To determine when a byte is available to read
from RCREG, poll the RCIDL bit (BAUDCON<6>)
for a low-to-high transition, or use the EUSART
Receive Interrupt Flag, RCIF (PIR1<5>).
Date Codes that pertain to this issue:
All engineering and production devices.
With the auto-wake-up option enabled by setting
the
(PIR1<5>) bit will become set on a high-to-low
transition on the RX pin. However, the WUE bit
may not clear within 1 T
tion on RX. While the WUE bit is set, reading the
receive buffer, RCREG, will not clear the RCIF
interrupt flag. Therefore, the first opportunity to
automatically clear RCIF by reading RCREG may
take longer than expected.
Work around
There are two work arounds available:
1. Clear the WUE bit in software after the wake-
2. Poll the WUE bit and read RCREG after the
Date Codes that pertain to this issue:
All engineering and production devices.
up event has occurred prior to reading the
receive buffer, RCREG.
WUE bit is automatically cleared.
WUE
RCIF can only be cleared by reading
RCREG
(BAUDCON<1>)
CY
of a low-to-high transi-
bit,
the
PIC18F2420/2520/4420/4520
RCIF
37. Module: MSSP
38. Module: MSSP
The MSSP configured in SPI Slave mode will
generate a write collision if SSPBUF is updated and
the previous SSPBUF contents have not been
transferred
Re-initializing the MSSP by clearing and setting the
SSPEN (SSPCON1<5>) bit prior to rewriting
SSPBUF will not prevent the error condition.
Work around
Prior to updating the SSPBUF register with a new
value, verify whether the previous contents were
transferred by reading the BF (SSPSTAT<0>) bit. If
the previous byte has not been transferred, update
SSPBUF and clear the WCOL (SSPCON1<7>) bit if
necessary.
Date Codes that pertain to this issue:
All engineering and production devices.
It has been observed that following a Power-on
Reset, I
configuring the SCL and SDA pins as either inputs
or outputs. This has only been seen in a few
unique system environments.
A test of a statistically significant sample of pre-
production systems, across the voltage and
current range of the application's power supply,
should indicate if a system is susceptible to this
issue.
Work around
Before configuring the module for I
1. Configure the SCL and SDA pins as outputs by
2. Force SCL and SDA low by clearing the
3. While keeping the LAT bits clear, configure
Once this is done, use the SSPCON1 and
SSPCON2 registers to configure the proper I
mode as before.
Date Codes that pertain to this issue:
All engineering and production devices.
clearing their corresponding TRIS bits.
corresponding LAT bits.
SCL and SDA as inputs by setting their TRIS
bits.
2
C mode may not initialize properly by just
to the shift register
.
DS80209H-page 11
2
C operation:
2
C