PIC18LF4321-I/ML Microchip Technology, PIC18LF4321-I/ML Datasheet - Page 5

• Manufacturer Part Number: PIC18LF4321-I/ML
• Description: 8 KB Flash, 512 RAM 44 QFN 8x8x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF4321-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

For PIC18F2685/4685 devices, the code memory
space extends from 0000h to 017FFFh (96 Kbytes) in
five 16-Kbyte blocks. For PIC18F2682/4682 devices,
the code memory space extends from 0000h to
0013FFFh (80 Kbytes) in four 16-Kbyte blocks.
Addresses, 0000h through 0FFFh, however, define a
“Boot Block” region that is treated separately from
Block 0. All of these blocks define code protection
boundaries within the code memory space.
The size of the Boot Block in PIC18F2685/4685 and
PIC18F2682/4682 devices can be configured as 1, 2 or
4K words (see
FIGURE 2-4:
 2010 Microchip Technology Inc.
Note:
3FFFFFh
01FFFFh
000000h
200000h
*
Sizes of memory areas are not to scale.
Boot Block size is determined by the BBSIZ<1:2> bits in the CONFIG4L register.
Unimplemented
Code Memory
Configuration
Read as ‘0’
and ID
Figure
Space
MEMORY MAP AND THE CODE MEMORY SPACE 
FOR PIC18F2685/4685 AND PIC18F2682/4682 DEVICES
2-4). This is done through the
Block 0
11/10
Block*
Boot
(PIC18F2685/4685)
Unimplemented
Reads all ‘0’s
PIC18F2XXX/4XXX FAMILY
96 Kbytes
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block*
Boot
01
MEMORY SIZE/DEVICE
Block 0
Block*
Boot
BBSIZ1:BBSIZ2
00
BBSIZ<2:1>
CONFIG4L. It is important to note that increasing the
size of the Boot Block decreases the size of Block 0.
TABLE 2-3:
PIC18F2682
PIC18F4682
PIC18F2685
PIC18F4685
Device
Block 0
11/10
Block*
Boot
bits
(PIC18F2682/4682)
Unimplemented
IMPLEMENTATION OF CODE
MEMORY
Reads all ‘0’s
in
Block 0
Block 1
Block 2
Block 3
Block 4
80 Kbytes
Block*
Boot
01
Code Memory Size (Bytes)
the
000000h-013FFFh (80K)
000000h-017FFFh (96K)
Configuration
Block 0
Block*
Boot
00
DS39622L-page 5
000000h
0007FFh
000800h
000FFFh
001000h
001FFFh
002000h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
010000h
013FFFh
014000h
017FFFh
01FFFFh
Address
Range
register,