PIC18LF2550T-I/SO Microchip Technology, PIC18LF2550T-I/SO Datasheet - Page 70
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PIC18LF2550T-I/SO
Manufacturer Part Number
PIC18LF2550T-I/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PCM18XR1.pdf
(438 pages)
3.PIC18F2221-ISO.pdf
(46 pages)
4.PIC18F2455-ISO.pdf
(14 pages)
5.PIC18F2455-ISO.pdf
(8 pages)
6.PIC18F2455-ISO.pdf
(26 pages)
Specifications of PIC18LF2550T-I/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
SPI, I2C, EAUSART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163025, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PCM18XR1 PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2455-ISO PDF datasheet #4
- PIC18F2455-ISO PDF datasheet #5
- PIC18F2455-ISO PDF datasheet #6
- Current page: 70 of 438
- Download datasheet (7Mb)
PIC18F2455/2550/4455/4550
5.3.5
The Special Function Registers (SFRs) are registers
used by the CPU and peripheral modules for controlling
the desired operation of the device. These registers are
implemented as static RAM in the data memory space.
SFRs start at the top of data memory and extend down-
ward to occupy the top segment of Bank 15, from F60h
to FFFh. A list of these registers is given in Table 5-1
and Table 5-2.
The SFRs can be classified into two sets: those
associated with the “core” device functionality (ALU,
Resets and interrupts) and those related to the
TABLE 5-1:
DS39632E-page 68
Note 1:
Address
FEDh POSTDEC0
FECh
FFEh
FFDh
FFCh
FFBh
FEFh
FEEh POSTINC0
FEBh
FEAh
FFFh
FFAh
FE9h
FE8h
FE7h
FE6h POSTINC1
FE5h POSTDEC1
FE4h
FE3h
FE2h
FE1h
FE0h
FF9h
FF8h
FF7h
FF6h
FF5h
FF4h
FF3h
FF2h
FF1h
FF0h
2:
3:
Not a physical register.
Unimplemented registers are read as ‘0’.
These registers are implemented only on 40/44-pin devices.
PREINC0
PREINC1
PLUSW0
PLUSW1
SPECIAL FUNCTION REGISTERS
TBLPTRU
TBLPTRH
TBLPTRL
INTCON2
INTCON3
STKPTR
PCLATU
PCLATH
INTCON
INDF0
INDF1
TABLAT
PRODH
PRODL
FSR0H
FSR1H
FSR0L
WREG
FSR1L
TOSU
TOSH
Name
TOSL
BSR
PCL
SPECIAL FUNCTION REGISTER MAP
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Address
FDDh POSTDEC2
FDCh PREINC2
FCDh
FCCh
FDFh
FDEh POSTINC2
FDBh
FDAh
FCFh
FCEh
FCBh
FCAh
FD9h
FD8h
FD7h
FD6h
FD5h
FD4h
FD3h
FD2h
FD1h
FD0h
FC9h
FC8h
FC7h
FC6h
FC5h
FC4h
FC3h
FC2h
FC1h
FC0h
PLUSW2
HLVDCON
SSPCON1
SSPCON2
OSCCON
WDTCON
SSPSTAT
ADRESH
ADCON0
ADCON1
ADCON2
SSPBUF
SSPADD
ADRESL
INDF2
STATUS
TMR0H
TMR1H
T0CON
T1CON
T2CON
FSR2H
TMR0L
TMR1L
FSR2L
RCON
Name
TMR2
—
PR2
(2)
(1)
(1)
(1)
(1)
(1)
Address
FBDh
FBCh
FBEh
FBBh
FBAh
FADh
FACh
FBFh
FAEh
FABh
FAAh
FB9h
FB8h
FB7h
FB6h
FB5h
FB4h
FB3h
FB2h
FB1h
FB0h
FAFh
FA9h
FA8h
FA7h
FA6h
FA5h
FA4h
FA3h
FA2h
FA1h
FA0h
ECCP1DEL
EECON2
BAUDCON
CCP1CON
CCP2CON
ECCP1AS
CVRCON
SPBRGH
CCPR1H
CCPR2H
EECON1
CCPR1L
CCPR2L
EEDATA
CMCON
RCREG
TMR3H
T3CON
SPBRG
TXREG
EEADR
TMR3L
RCSTA
TXSTA
Name
IPR2
PIR2
PIE2
—
—
—
—
—
peripheral functions. The Reset and interrupt registers
are described in their respective chapters, while the
ALU’s STATUS register is described later in this
section. Registers related to the operation of a
peripheral feature are described in the chapter for that
peripheral.
The SFRs are typically distributed among the
peripherals whose functions they control. Unused SFR
locations are unimplemented and read as ‘0’s.
(2)
(2)
(2)
(2)
(2)
(1)
Address
F9Dh
F9Ch
F8Dh
F8Ch
F9Eh
F9Bh
F9Ah
F8Eh
F8Bh
F8Ah
F9Fh
F98h
F94h
F93h
F90h
F8Fh
F86h
F81h
F99h
F97h
F96h
F95h
F92h
F91h
F89h
F88h
F87h
F85h
F84h
F83h
F82h
F80h
OSCTUNE
PORTD
TRISE
TRISD
LATD
PORTE
PORTC
PORTB
LATE
PORTA
TRISC
TRISB
TRISA
Name
LATC
LATB
IPR1
PIR1
LATA
PIE1
—
—
—
—
—
—
—
—
—
—
—
—
—
© 2009 Microchip Technology Inc.
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(3)
(3)
(3)
(3)
(3)
Address
F7Dh
F7Ch
F6Dh
F6Ch
F7Eh
F7Bh
F7Ah
F6Eh
F6Bh
F6Ah
F7Fh
F79h
F78h
F77h
F76h
F75h
F74h
F73h
F72h
F71h
F70h
F6Fh
F69h
F68h
F67h
F66h
F65h
F64h
F63h
F62h SPPDATA
F61h
F60h
SPPCON
SPPEPS
SPPCFG
UFRMH
UADDR
UFRML
UEP15
UEP14
UEP13
UEP12
UEP10
UEP11
USTAT
UCON
Name
UCFG
UEP9
UEP8
UEP7
UEP6
UEP5
UEP4
UEP3
UEP2
UEP1
UEP0
UEIR
UEIE
—
—
UIE
UIR
(2)
(2)
(3)
(3)
(3)
(3)
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