PIC18LF2423-I/ML Microchip Technology, PIC18LF2423-I/ML Datasheet
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PIC18LF2423-I/ML
Specifications of PIC18LF2423-I/ML
Related parts for PIC18LF2423-I/ML
PIC18LF2423-I/ML Summary of contents
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... See Figure 5-1 for more information. 2: All power supply (V ) and ground (V DD 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY ICSP method is slightly different than the high-voltage method and these differences are noted where applicable. This programming PIC18F2XXX/4XXX family devices in all package types ...
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... RA1 3 RA2 4 RA3 5 RA4 6 RA5 7 RE0 8 RE1 9 RE2 OSC1 13 OSC2 14 RC0 15 RC1 16 RC2 17 RC3 18 RD0 19 RD1 20 2010 Microchip Technology Inc. RB7/PGD 28 27 RB6/PGC RB5/PGM 26 25 RB4 RB3 24 RB2 23 RB1 22 RB0 RC7 RC6 17 RC5 16 RC4 15 21 RB3 20 RB2 RB1 19 RB0 18 17 ...
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... PIC18F4580 • PIC18F4450 • PIC18F4585 • PIC18F4455 • PIC18F4610 • PIC18F4458 • PIC18F4620 • PIC18F4480 • PIC18F4680 • PIC18F4510 • PIC18F4682 • PIC18F4520 • PIC18F4685 • PIC18F4515 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY RC7 1 RD4 2 RD5 3 RD6 4 RD7 5 V PIC18F4XXX ...
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... Reads all ‘0’s Code Memory Size (Bytes) 000000h-00BFFFh (48K) 000000h-00FFFFh (64K) Address Range 01 00 000000h Boot Block* Boot 0007FFh 000800h Block* 000FFFh 001000h 001FFFh Block 0 002000h Block 0 003FFFh 004000h Block 1 007FFFh 008000h Block 2 00BFFFh 00C000h 00FFFFh 01FFFFh 2010 Microchip Technology Inc. ...
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... Note: Sizes of memory areas are not to scale. * Boot Block size is determined by the BBSIZ<1:2> bits in the CONFIG4L register. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY BBSIZ<2:1> CONFIG4L important to note that increasing the size of the Boot Block decreases the size of Block 0. TABLE 2-3: ...
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... Reads all ‘0’s Code Memory Size (Bytes) 000000h-005FFFh (24K) 000000h-007FFFh (32K) 24 Kbytes Address Range 000000h Boot Block 0007FFh 000800h Block 0 001FFFh 002000h Block 1 003FFFh 004000h Block 2 005FFFh 006000h 007FFFh Unimplemented Reads all ‘0’s 1FFFFFh 2010 Microchip Technology Inc. ...
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... FOR PIC18FX4X0/X4X3 DEVICES 000000h Code Memory 1FFFFFh Unimplemented Read as ‘0’ 200000h Configuration and ID Space 3FFFFFh Note: Sizes of memory areas are not to scale. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY TABLE 2-5: IMPLEMENTATION OF CODE MEMORY Device PIC18F2410 PIC18F2420 PIC18F2423 PIC18F2450 PIC18F4410 PIC18F4420 PIC18F4450 ...
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... Unimplemented Reads all ‘0’s Unimplemented Reads all ‘0’s Code Memory Size (Bytes) 000000h-003FFFh (16K) 000000h-007FFFh (32K) Address Range 0 000000h Boot Block* 0007FFh 000800h 000FFFh 001000h Block 0 001FFFh 002000h 003FFFh 004000h 005FFFh 006000h 007FFFh 01FFFFh 2010 Microchip Technology Inc. ...
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... Space 3FFFFFh Note: Sizes of memory areas are not to scale. * Boot Block size is determined by the BBSIZ<1:0> bits in the CONFIG4L register. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY CONFIG4L (see increasing the size of the Boot Block decreases the size of Block 0. TABLE 2-7: Device ...
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... CONFIG1L 300000h CONFIG1H 300001h CONFIG2L 300002h CONFIG2H 300003h CONFIG3L 300004h CONFIG3H 300005h CONFIG4L 300006h CONFIG4H 300007h CONFIG5L 300008h CONFIG5H 300009h CONFIG6L 30000Ah CONFIG6H 30000Bh CONFIG7L 30000Ch CONFIG7H 30000Dh Device ID1 3FFFFEh Device ID2 3FFFFFh 2010 Microchip Technology Inc. TBLPTRL Addr[7:0] ...
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... Verify Configuration Bits Done Note 1: Selected devices only, see “Data EEPROM Programming”. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY 2.5 Entering and Exiting High-Voltage ICSP Program/Verify Mode As shown in Program/Verify mode is entered by holding PGC and PGD low and then raising MCLR/V Section 3 ...
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... Command 1101 Table 2-9. The 4-bit command COMMANDS FOR PROGRAMMING 4-Bit Description Command 0000 0010 1000 1001 1010 1011 1100 1101 1110 1111 SAMPLE COMMAND SEQUENCE Data Core Instruction Payload Table Write, post-increment by 2 2010 Microchip Technology Inc. ...
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... ICPRT Configuration bit is set. When the V is seen on the MCLR/V /RE3 pin prior to applying IH PP TABLE 2-10: ICSP™ EQUIVALENT PINS Pin Name Pin Name Pin Type MCLR/V /RE3 RB6 PGC RB7 PGD I/O Legend Input Output Power 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY ...
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... F6 MOVWF TBLPTRL 8F 8F Write 8F8Fh TO 3C0004h to erase entire device NOP 00 00 Hold PGD low until erase completes. BULK ERASE FLOW Start Write 3F3Fh to 3C0005h Write 8F8Fh to 3C0004h to Erase Entire Device Delay P11 + P10 Time Done 2010 Microchip Technology Inc. ...
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... After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by Parameter P10 to allow high-voltage discharge of the memory array. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY determined that a data EEPROM erase (selected devices only, see EEPROM Programming” ...
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... NOP – hold PGC high for time P9 and low for time P10. Start Configure Device for Row Erases Start Erase Sequence and Hold PGC High for Time P9 Hold PGC Low for Time P10 All No rows done? Done Addr = 0 Yes 2010 Microchip Technology Inc. ...
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... To continue writing data, repeat Steps 2 through 4, where the Address Pointer is incremented each iteration of the loop. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY After PGC is brought low, the programming sequence is terminated. PGC must be held low for the time specified by Parameter P10 to allow high-voltage discharge of the memory array ...
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... Yes Start Write Sequence and Hold PGC High until Done and Wait P9 Hold PGC Low for Time P10 All No locations done? Yes Done P5A 4-Bit Command PGD = Input ) 1111 P10 Programming Time 16-Bit Data Payload 2010 Microchip Technology Inc. ...
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... The write cycle must be repeated enough times to completely rewrite the contents of the erase buffer. Step 7: Disable writes. 0000 94 A6 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY The appropriate number of bytes required for the erase buffer must be read out of code memory (as described in Section 4.2 “ ...
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... MOVF EECON1 PGD = Input PROGRAM DATA FLOW Start Set Address Set Data Enable Write Start Write Sequence No WR bit clear? Yes No Done? Yes Done P10 16-Bit Data Payload P5A Shift Out Data (see Figure 4-4) PGD = Output 2010 Microchip Technology Inc. ...
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... Step 7: Hold PGC low for time P10. Step 8: Disable writes. 0000 94 A6 Repeat Steps 2 through 8 to write more data. Note 1: See Figure 4-4 for details on shift out data timing. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY Core Instruction BCF EECON1, EEPGD BCF EECON1, CFGS MOVLW < ...
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... Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and post-increment address by 2. Write 2 bytes and start programming. NOP - hold PGC high for time P9 and low for time P10. Section 3.2.1 “Modifying Code 2010 Microchip Technology Inc. ...
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... Configuration Address Program LSB Delay P9 and P10 Time for Write Done 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY 3.6 Configuration Bits Programming should be Unlike code memory, the Configuration bits are programmed a byte at a time. The Table Write, Begin Programming 4-bit command (‘1111’) is used, but only 8 bits of the following 16-bit payload will be written ...
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... ID and Configuration registers. Core Instruction MOVLW Addr[21:16] MOVWF TBLPTRU MOVLW <Addr[15:8]> MOVWF TBLPTRH MOVLW <Addr[7:0]> MOVWF TBLPTRL TBLRD *+ P14 LSb Shift Data Out PGD = Output 4-1). This operation also increments P5A 4 MSb Fetch Next 4-Bit Command PGD = Input 2010 Microchip Technology Inc. ...
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... All No code memory verified? Yes 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY The Table Pointer must be manually set to 200000h (base address of the ID locations) once the code memory has been verified. The post-increment feature of the Table Read 4-bit command may not be used to increment the Table Pointer beyond the code memory space ...
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... EECON1, CFGS MOVLW <Addr> MOVWF EEADR MOVLW <AddrH> MOVWF EEADRH BSF EECON1, RD MOVF EEDATA MOVWF TABLAT NOP (1) Shift Out Data READ DATA EEPROM FLOW Start Set Address Read Byte Move to TABLAT Shift Out Data No Done? Yes Done 2010 Microchip Technology Inc. ...
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... Blank Checking a device merely means to verify that all bytes read as FFh, except the Configuration bits. Unused (reserved) Configuration bits will read ‘0’ (pro- grammed). Refer to Figure 4-5 for blank configuration expect data for the various PIC18F2XXX/4XXX family devices. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY ...
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... See Table 5-2 for a complete list of Device ID values. FIGURE 5-1: READ DEVICE ID WORD FLOW Start Set TBLPTR = 3FFFFE Read Low Byte with Post-Increment Read High Byte with Post-Increment Done 2010 Microchip Technology Inc. ...
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... DEVID registers are read-only and cannot be programmed by the user. 7: Implemented on all devices with the exception of the PIC18FXX8X and PIC18F2450/4450 devices. 8: Implemented on PIC18F2450/4450 devices only. 9: Implemented on PIC18F2682/2685 and PIC18F4682/4685 devices only. 10: Implemented on PIC18F2685/4685 devices only. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY Bit 5 Bit 4 Bit 3 Bit 2 USBDIV CPUDIV1 ...
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... Microchip Technology Inc. DEVID1 (1) (2) (1) (2) (1) (2) (1) (2) ...
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... Note 1: The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0. 2: Not available in PIC18FXX8X and PIC18F2450/4450 devices. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY Device ID Value DEVID2 0Ch ...
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... Brown-out Reset is enabled in hardware only (SBOREN is disabled Brown-out Reset is enabled in hardware only and disabled in Sleep mode SBOREN is disabled Brown-out Reset is enabled and controlled by software (SBOREN is enabled Brown-out Reset is disabled in hardware and software Power-up Timer Enable bit 1 = PWRT is disabled 0 = PWRT is enabled 2010 Microchip Technology Inc. ...
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... The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0. 2: Not available in PIC18FXX8X and PIC18F2450/4450 devices. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY Description Watchdog Timer Postscaler Select bits ...
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... Block 5 is code-protected Code Protection bit (Block 4 code memory area) (PIC18F2682/2685 and PIC18F4682/4685 devices only Block 4 is not code-protected 0 = Block 4 is code-protected Code Protection bit (Block 3 code memory area Block 3 is not code-protected 0 = Block 3 is code-protected 2010 Microchip Technology Inc. ...
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... The BBSIZ bits, BBSIZ<1:0> and BBSIZ<2:1> bits, cannot be changed once any of the following code-protect bits are enabled: CPB or CP0, WRTB or WRT0, EBTRB or EBTR0. 2: Not available in PIC18FXX8X and PIC18F2450/4450 devices. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY Description Code Protection bit (Block 2 code memory area) ...
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... These bits are used with the DEV<10:3> bits in the DEVID2 register to identify part number. Revision ID bits These bits are used to indicate the revision of the device. The REV4 bit is sometimes used to fully specify the device type. 2010 Microchip Technology Inc. ...
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... An option to not include the data EEPROM information may be provided. When embedding data EEPROM information in the hex file, it should start at address, F00000h. Microchip Technology Inc. believes that this feature is important for the benefit of the end customer. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY 5 ...
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... Microchip Technology Inc. ...
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... PIC18F4685 96K 44 000FFF 003FFF 007FFF 00BFFF 00FFFF 013FFF 017FFF 001FFF Legend: — = unimplemented. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY Ending Address Boot Block — — — 2048 — — — 2048 2048 — ...
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... CF 1F PIC18F2610 PIC18F2620 PIC18F2680 PIC18F2682 PIC18F2685 PIC18F4221 PIC18F4321 PIC18F4410 PIC18F4420 PIC18F4423 PIC18F4450 PIC18F4455 PIC18F4458 PIC18F4480 PIC18F4510 PIC18F4515 PIC18F4520 PIC18F4523 PIC18F4525 PIC18F4550 PIC18F4553 PIC18F4580 PIC18F4585 PIC18F4610 Legend: Shaded cells are unimplemented. DS39622L-page 40 Configuration Word (CONFIGxx Address (30000xh 2010 Microchip Technology Inc. ...
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... TABLE 5-5: CONFIGURATION WORD MASKS FOR COMPUTING CHECKSUMS (CONTINUED Device PIC18F4620 PIC18F4680 PIC18F4682 PIC18F4685 Legend: Shaded cells are unimplemented. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY Configuration Word (CONFIGxx Address (30000xh DS39622L-page 41 ...
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... V Externally timed, Row Erases and all writes V Self-timed, Bulk Erases only (Note 3) A (Note meet AC specifications s (Notes 5.0V DD Externally timed the oscillator period. For OSC 2010 Microchip Technology Inc. ...
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... T is the instruction cycle time specific values, refer to the Electrical Characteristics section of the device data sheet for the particular device. 2: When ICPRT = 1, this specification also applies to ICV 3: At 0°C-50°C. 2010 Microchip Technology Inc. PIC18F2XXX/4XXX FAMILY Min Max 4 /RE3 /RE3 ...
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... PIC18F2XXX/4XXX FAMILY NOTES: DS39622L-page 44 2010 Microchip Technology Inc. ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 2010 Microchip Technology Inc. 08/04/10 ...