PIC18LF2420T-I/ML Microchip Technology, PIC18LF2420T-I/ML Datasheet - Page 138

28 PIN, 16 KB ENHFLASH, 768 B RAM, 25 I/O PB FREE,

PIC18LF2420T-I/ML

Manufacturer Part Number
PIC18LF2420T-I/ML
Description
28 PIN, 16 KB ENHFLASH, 768 B RAM, 25 I/O PB FREE,
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18LF2420T-I/ML

Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF2420T-I/ML
Manufacturer:
MICROCHIP
Quantity:
1 001
PIC18F2420/2520/4420/4520
14.1
Timer3 can operate in one of three modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
FIGURE 14-1:
FIGURE 14-2:
DS39631E-page 136
T1OSO/T13CKI
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T13CKI/T1OSO
Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Timer3 Operation
T1OSI
T1OSI
CCP1/CCP2 Select from T3CON<6,3>
CCP1/CCP2 Select from T3CON<6,3>
CCP1/CCP2 Special Event Trigger
CCP1/CCP2 Special Event Trigger
Timer1 Oscillator
T1OSCEN
T3CKPS<1:0>
T3SYNC
TMR3ON
Timer1 Oscillator
TIMER3 BLOCK DIAGRAM
T1OSCEN
T3CKPS<1:0>
T3SYNC
TMR3ON
TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
(1)
(1)
TMR3CS
TMR3CS
Internal
Clock
Clock
F
Internal
F
OSC
OSC
/4
/4
1
0
1
0
Timer1 Clock Input
Timer1 Clock Input
Clear TMR3
Clear TMR3
Prescaler
Prescaler
1, 2, 4, 8
1, 2, 4, 8
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
cycle (F
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
As with Timer1, the RC1/T1OSI and RC0/T1OSO/
T13CKI pins become inputs when the Timer1 oscillator
is enabled. This means the values of TRISC<1:0> are
ignored and the pins are read as ‘0’.
2
2
OSC
TMR3L
TMR3L
/4). When the bit is set, Timer3 increments
8
Sleep Input
Sleep Input
8
Synchronize
Synchronize
Detect
Detect
High Byte
High Byte
TMR3H
TMR3
TMR3
8
© 2008 Microchip Technology Inc.
8
8
Internal Data Bus
1
0
1
0
Read TMR1L
Write TMR1L
on Overflow
on Overflow
TMR3IF
TMR3IF
Set
Set
Timer3
On/Off
Timer3
On/Off

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