PIC18LF2221-I/ML Microchip Technology, PIC18LF2221-I/ML Datasheet - Page 388
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PIC18LF2221-I/ML
Manufacturer Part Number
PIC18LF2221-I/ML
Description
4 KB Flash, 512 RAM 28 QFN 6x6mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(402 pages)
2.PIC18F2221-ISO.pdf
(8 pages)
3.PIC18F2221-ISO.pdf
(30 pages)
4.PIC18F2221-ISO.pdf
(46 pages)
5.PIC18LF2221-IML.pdf
(394 pages)
Specifications of PIC18LF2221-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF2221-I/ML
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18LF2221-I/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F4321 FAMILY
RETLW ............................................................................. 304
RETURN .......................................................................... 305
Return Address Stack ........................................................ 54
Return Stack Pointer (STKPTR) ........................................ 55
Revision History ............................................................... 375
RLCF ................................................................................ 305
RLNCF ............................................................................. 306
RRCF ............................................................................... 306
RRNCF ............................................................................. 307
S
SCK .................................................................................. 161
SDI ................................................................................... 161
SDO ................................................................................. 161
SEC_IDLE Mode ................................................................ 38
SEC_RUN Mode ................................................................ 34
Serial Clock, SCK ............................................................. 161
Serial Data In (SDI) .......................................................... 161
Serial Data Out (SDO) ..................................................... 161
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 307
Single-Supply ICSP Programming.
Slave Select (SS) ............................................................. 161
SLEEP .............................................................................. 308
Sleep
Software Simulator (MPLAB SIM) .................................... 324
Special Event Trigger. See Compare (CCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ............................................ 253
Special Function Registers ................................................ 62
Special ICPORT Features ................................................ 271
SPI Mode (MSSP)
SS .................................................................................... 161
SSPOV ............................................................................. 195
SSPOV Status Flag .......................................................... 195
SSPSTAT Register
Stack Full/Underflow Resets .............................................. 56
SUBFSR ........................................................................... 319
SUBFWB .......................................................................... 308
SUBLW ............................................................................ 309
SUBULNK ........................................................................ 319
SUBWF ............................................................................ 309
SUBWFB .......................................................................... 310
SWAPF ............................................................................ 310
DS39689A-page 386
Associated Registers ................................................. 54
OSC1 and OSC2 Pin States ...................................... 32
Map ............................................................................ 62
Associated Registers ............................................... 169
Bus Mode Compatibility ........................................... 169
Effects of a Reset ..................................................... 169
Enabling SPI I/O ...................................................... 165
Master Mode ............................................................ 166
Master/Slave Connection ......................................... 165
Operation ................................................................. 164
Operation in Power-Managed Modes ...................... 169
Serial Clock .............................................................. 161
Serial Data In ........................................................... 161
Serial Data Out ........................................................ 161
Slave Mode .............................................................. 167
Slave Select ............................................................. 161
Slave Select Synchronization .................................. 167
SPI Clock ................................................................. 166
Typical Connection .................................................. 165
R/W Bit ............................................................. 175, 177
Advance Information
T
Table Reads/Table Writes ................................................. 56
TBLRD ............................................................................. 311
TBLWT ............................................................................. 312
Time-out in Various Situations (table) ................................ 45
Timer0 .............................................................................. 123
Timer1 .............................................................................. 127
Timer2 .............................................................................. 133
Timer3 .............................................................................. 135
Timing Diagrams
Associated Registers ............................................... 125
Operation ................................................................. 124
Overflow Interrupt .................................................... 125
Prescaler ................................................................. 125
Prescaler Assignment (PSA Bit) .............................. 125
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 125
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 124
Source Edge Select (T0SE Bit) ............................... 124
Source Select (T0CS Bit) ......................................... 124
Switching Prescaler Assignment ............................. 125
16-Bit Read/Write Mode .......................................... 129
Associated Registers ............................................... 131
Interrupt ................................................................... 130
Operation ................................................................. 128
Oscillator .......................................................... 127, 129
Overflow Interrupt .................................................... 127
Resetting, Using the CCP Special
Special Event Trigger (ECCP) ................................. 148
TMR1H Register ...................................................... 127
TMR1L Register ....................................................... 127
Use as a Real-Time Clock ....................................... 130
Associated Registers ............................................... 134
Interrupt ................................................................... 134
Operation ................................................................. 133
Output ...................................................................... 134
PR2 Register ................................................... 144, 149
TMR2-to-PR2 Match Interrupt ......................... 144, 149
16-Bit Read/Write Mode .......................................... 137
Associated Registers ............................................... 137
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow Interrupt ............................................ 135, 137
Special Event Trigger (CCP) ................................... 137
TMR3H Register ...................................................... 135
TMR3L Register ....................................................... 135
A/D Conversion ........................................................ 364
Acknowledge Sequence .......................................... 198
Asynchronous Reception ......................................... 219
Asynchronous Transmission .................................... 216
Asynchronous Transmission (Back to Back) ........... 216
Automatic Baud Rate Calculation ............................ 214
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 220
Baud Rate Generator with Clock Arbitration ............ 192
BRG Overflow Sequence ......................................... 214
BRG Reset Due to SDA Arbitration
Brown-out Reset (BOR) ........................................... 350
Layout Considerations ..................................... 130
Low-Power Option ........................................... 129
Event Trigger ................................................... 130
Normal Operation ............................................ 220
During Start Condition ..................................... 201
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