PIC18LF1330-I/ML Microchip Technology, PIC18LF1330-I/ML Datasheet - Page 2
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PIC18LF1330-I/ML
Manufacturer Part Number
PIC18LF1330-I/ML
Description
Microcontroller
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.AC162078.pdf
(318 pages)
3.PIC18F1230-ISO.pdf
(6 pages)
4.PIC18F1230-ISO.pdf
(12 pages)
5.PIC18F1230-ISO.pdf
(4 pages)
Specifications of PIC18LF1330-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC18F1230/1330
3. Module: Enhanced Universal
REGISTER 14-3:
DS80352B-page 2
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 5
bit 4
ABDOVF
The BAUDCON register is changed to add one bit
and rename another:
• Added bit – Bit 5, previously unimplemented, is
• Renamed bit – Bit 4, previously SCKP, is now
R/W-0
now RXDTP
TXCKP
Synchronous Receiver
Transmitter (EUSART)
RXDTP: Received Data Polarity Select bit
Asynchronous mode:
1 = RX data is inverted
0 = RX data is not inverted
Synchronous mode:
Unused in this mode
TXCKP: Clock and Data Polarity Select bit
Asynchronous mode:
1 = TX data is inverted
0 = TX data is not inverted
Synchronous mode:
1 = CK clocks are inverted
0 = CK clocks are not inverted
RCIDL
R-1
BAUDCON: BAUD RATE CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
RXDTP
R/W-0
TXCKP
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
BRG16
R/W-0
The TXCKP and RXDTP bits allow the Asynchro-
nous mode TX and RX signals to be inverted
(polarity reversed). RXDTP has no effect on the
Synchronous mode DT signal.
The register table and new bit descriptions appear
as shown.
U-0
—
© 2008 Microchip Technology Inc.
x = Bit is unknown
R/W-0
WUE
ABDEN
R/W-0
bit 0