PIC18F86J60T-I/PT Microchip Technology, PIC18F86J60T-I/PT Datasheet - Page 2
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PIC18F86J60T-I/PT
Manufacturer Part Number
PIC18F86J60T-I/PT
Description
64KB Flash, 12KB RAM, 10BASE-T Ethernet 80 TQFP 12x12x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F86J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 15x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
55
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 15 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F86J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
PIC18F97J60 FAMILY
3. Module: I/O (PORTJ) and External
DS80292D-page 2
In
(CONFIG3L<EMB1:0> = 00, 01 or 10), each
control signal on PORTJ is supposed to be driven
to its Idle state. However, the control signals on
PORTJ pins go to a high-impedance state for a
brief interval after a MCLR Reset. The brief loss of
control signals may cause the corruption of data in
memory devices connected to the External
Memory Bus (EMB).
Work around
To maintain the default states on the control lines,
use pull-up or pull-down resistors on all PORTJ
pins (pull-down on PORTJ<4,0>, pull-up on all
others).
Date Codes that pertain to this issue:
All engineering and production devices.
Note:
an
Memory Bus
This issue is only applicable to the
100-pin device.
Extended
Microcontroller
mode
4. Module: Ethernet (Buffer Memory)
EXAMPLE 1:
The receive hardware may corrupt the circular
receive buffer (including the Next Packet Pointer
and receive status vector fields) when an even value
is programmed into the ERXRDPTH:ERXRDPTL
registers.
Work around
Ensure that only odd addresses are written to the
ERXRDPT registers. Assuming that ERXND con-
tains an odd value, many applications can derive a
suitable value to write to ERXRDPT by subtracting 1
from the Next Packet Pointer (a value always
ensured to be even because of hardware padding)
and then compensating for a potential ERXST to
ERXND wraparound.
Assuming that the receive buffer area does not
span the 1FFFh to 0000h memory boundary, the
logic in Example 1 will ensure that ERXRDPT is
programmed with an odd value.
Date Codes that pertain to this issue:
All engineering and production devices.
if (Next Packet Pointer – 1 < ERXST) or
(Next Packet Pointer – 1 > ERXND)
ERXRDPT = ERXND
ERXRDPT = Next Packet Pointer – 1
then:
else:
© 2008 Microchip Technology Inc.