PIC18F86J60T-I/PT Microchip Technology, PIC18F86J60T-I/PT Datasheet - Page 3
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PIC18F86J60T-I/PT
Manufacturer Part Number
PIC18F86J60T-I/PT
Description
64KB Flash, 12KB RAM, 10BASE-T Ethernet 80 TQFP 12x12x1mm T/R
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F66J65-IPT.pdf
(8 pages)
2.PIC18F66J65-IPT.pdf
(480 pages)
3.PIC18F66J65-IPT.pdf
(4 pages)
4.PIC18F66J65-IPT.pdf
(10 pages)
Specifications of PIC18F86J60T-I/PT
Core Processor
PIC
Core Size
8-Bit
Speed
41.667MHz
Connectivity
Ethernet, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
55
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Ram Size
3808 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 15x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TFQFP
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3808 B
Interface Type
Display Driver, Ethernet, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
41.667 MHz
Number Of Programmable I/os
55
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM183033
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 15 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162064 - HEADER INTFC MPLABICD2 64/80/100AC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F86J60T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
4. Module: Ethernet (Buffer Memory)
EXAMPLE 1:
5. Module: Ethernet (MIIM)
2010 Microchip Technology Inc.
The receive hardware may corrupt the circular
receive buffer (including the Next Packet Pointer
and receive status vector fields) when an
even
ERXRDPTH:ERXRDPTL registers.
Work around
Ensure that only odd addresses are written to the
ERXRDPT registers. Assuming that ERXND con-
tains an odd value, many applications can derive
a suitable value to write to ERXRDPT by subtract-
ing 1 from the Next Packet Pointer (a value
always ensured to be even because of hardware
padding) and then compensating for a potential
ERXST to ERXND wraparound.
Assuming that the receive buffer area does not
span the 1FFFh to 0000h memory boundary, the
logic in
programmed with an odd value.
Affected Silicon Revisions
When writing to any PHY register through the MIIM
interface’s MIWRL and MIWRH registers, the low
byte actually written to the PHY register may be
corrupted. The corruption occurs when the
following actions are taken:
• The application writes to MIWRL
• The PIC
• The application writes to MIWRH
For example, the following sequence will result in
a corrupted write to a PHY register:
In this example, 0xCF5 and 0xCF6 are GPR
memory locations that the application wishes to
write to the current PHY register defined by the
if (Next Packet Pointer – 1 < ERXST) or
(Next Packet Pointer – 1 > ERXND)
ERXRDPT = ERXND
ERXRDPT = Next Packet Pointer – 1
A0
X
that reads or writes to any memory address that
has the Least Significant six address bits of 36h
(‘b110110)
MOVFF
NOP
MOVFF
then:
else:
Example 1
value
A1
X
®
MCU core executes any instruction
A2
X
is
will ensure that ERXRDPT is
0xCF5, MIWRL
0xCF6, MIWRH
A3
programmed
X
into
the
PIC18F97J60 FAMILY
MIREGADR SFR. When the PIC MCU core
reads from
(‘b110011110110), the value originally written to
MIWRL will be corrupted.
Work around 1
Ensure that following a write to MIWRL, the firm-
ware does not access any of the problem memory
locations prior to writing to MIWRH. After finished
writing to MIWRH, normal operation can resume.
If interrupts are enabled, disable them prior to writ-
ing to MIWRL and MIWRH to prevent an Interrupt
Service Routine (ISR) from performing any reads
or writes to a problem memory address.
Special care must be taken to ensure that the
source data to be written to MIWRH does not
result in a problem memory access.
The following PHY write sequence avoids the
problem:
1. Copy the low byte to be written to the PHY into
2. Copy the high byte to be written to the PHY into
3. Disable all interrupts by clearing GIEH and
4. Move PRODL into MIWRL.
5. Wait one instruction cycle as required by the
6. Move PRODH into MIWRH.
7. Enable all interrupts that are needed by
Work around 2
If you cannot disable interrupts, as specified in
Work around 1, because the application cannot
tolerate interrupt latency variations:
• Perform the write (with interrupts enabled), but
• Verify the correct values were written by
reading the PHY register
the PRODL register.
PRODL is at address, FF3h, and not subject to
the memory address issue.
the PRODH register.
PRODH is at address, FF4h, and not subject to
the memory address issue.
GIEL in the INTCON register.
MAC host interface logic.
restoring GIEH and GIEL in INTCON.
the
GPR
at
address,
DS80433C-page 3
0xCF6