PIC18F86J16-I/PT Microchip Technology, PIC18F86J16-I/PT Datasheet - Page 133

• Manufacturer Part Number: PIC18F86J16-I/PT
• Description: 96KB Flash, 3936 Bytes RAM, 10 MIPS, 67 I/O, NanoWatt 80 TQFP 12x12x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F86J16-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 96KB (48K x 16)
• Program Memory Type: FLASH
• Ram Size: 3930 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 15x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3904 B
• Interface Type: EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 68
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183022, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 15 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162091 - HEADER MPLAB ICD2 18F87J11 64/80MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC164328 - MODULE SKT FOR 80TQFP
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 10-4:
© 2009 Microchip Technology Inc.
RA0/AN0
RA1/AN1
RA2/AN2/V
RA3/AN3/V
RA4/PMD5/
T0CKI/
RA5/PMD4/AN4
OSC2/CLKO/
RA6
OSC1/CLKI/
RA7
Legend:
Note 1:
Pin Name
REF
REF
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate PMP configuration when the PMPMX Configuration bit is ‘0’; available on 80-pin devices only.
-
+
Function
PORTA FUNCTIONS
PMD5
PMD4
V
T0CKI
OSC2
CLKO
OSC1
V
CLKI
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
RA6
RA7
REF
REF
+
(1)
(1)
-
Setting
TRIS
0
1
1
0
1
1
0
1
1
1
0
1
1
1
0
1
x
x
x
0
1
x
x
1
x
x
0
1
x
x
0
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
TTL
DIG
TTL
I/O
ST
ST
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
A/D input channel 0. Default input configuration on POR; does not
affect digital output.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
A/D input channel 1. Default input configuration on POR; does not
affect digital output.
LATA<2> data output; not affected by analog input. Disabled when
CV
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CV
A/D input channel 2. Default input configuration on POR; not affected
by analog output.
A/D low reference voltage input.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3. Default input configuration on POR.
A/D high reference voltage input.
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Parallel Master Port data output.
Parallel Master Port data output.
Timer0 clock input.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
Parallel Master Port data output.
Parallel Master Port data output.
A/D input channel 4. Default configuration on POR.
Main oscillator feedback output connection (HS and HSPLL modes).
System cycle clock output, F
modes).
LATA<6> data output; disabled when FOSC2 Configuration bit is set.
PORTA<6> data input; disabled when FOSC2 Configuration bit is set.
Main oscillator input connection (HS and HSPLL modes).
Main external clock source input (EC and ECPLL modes).
LATA<7> data output; disabled when FOSC2 Configuration bit is set.
PORTA<7> data input; disabled when FOSC2 Configuration bit is set.
REF
output enabled.
PIC18F87J11 FAMILY
REF
output enabled.
OSC
Description
/4 (EC, ECPLL, INTIO1 and INTPLL1
DS39778D-page 133