PIC18F6680-E/PT Microchip Technology, PIC18F6680-E/PT Datasheet - Page 17

• Manufacturer Part Number: PIC18F6680-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6680-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3
Data EEPROM is accessed one byte at a time via an
Address Pointer (register pair, EEADR:EEADRH) and
a data latch (EEDATA). Data EEPROM is written by
loading EEADR:EEADRH with the desired memory
location, EEDATA with the data to be written and initiat-
ing a memory write by appropriately configuring the
EECON1 and EECON2 registers. A byte write auto-
matically erases the location and writes the new data
(erase-before-write).
When using the EECON1 register to perform a data
EEPROM write, both the EEPGD and CFGS bits must
be cleared (EECON1<7:6> = 00). The WREN bit must
be set (EECON1<2> = 1) to enable writes of any sort,
and this must be done prior to initiating a write
sequence. The write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit be set only when absolutely
necessary.
To help prevent inadvertent writes when using the
EECON1 register, EECON2 is used to “enable” the WR
bit. This register must be sequentially loaded with 55h
and then AAh immediately prior to asserting the WR bit
in order for the write to occur.
The write begins on the falling edge of the 4th PGC
after the WR bit is set. It ends when the WR bit is
cleared by hardware.
After the programming sequence terminates, PGC must
still be held low for the time specified by parameter P10
to allow high-voltage discharge of the memory array.
FIGURE 3-8:
 2010 Microchip Technology Inc.
PGC
PGD
Poll WR Bit
4-Bit Command
Data EEPROM Programming
1
0
2
0
3
0
4
0
PGC
PGD
P5
DATA EEPROM WRITE TIMING
BSF EECON1, WR
1
4-Bit Command
1
0
2
2
0
15 16
3
0
4
0
P5A
P5
MOVF EECON1, W, 0
1
2
15 16
PGD = Input
PGD = Input
P5A
4-Bit Command
Poll WR Bit, Repeat Until Clear
1
0
FIGURE 3-7:
2
0
3
0
(see below)
4
0
PIC18FXX80/XX85
P5
MOVWF TABLAT
1
No
2
Unlock Sequence
15 16
AAh – EECON2
55h – EECON2
Enable Write
Set Address
PROGRAM DATA FLOW
Start Write
Sequence
Set Data
WR bit
Clear?
Done
Done
P5A
Start
?
Yes
Yes
(see Figure 4-4)
Shift Out Data
PGD = Output
DS39606E-page 17
No
P10
16-Bit Data
Payload
1
n
2
n