PIC18F4520-E/PT Microchip Technology, PIC18F4520-E/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F4520-E/PT
• Description: 44 PIN, 32 KB ENH FLASH, 3804 RAM, 36 I/O, PB FREE,
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4520-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 18-3:
4. Module: 10-Bit Analog-to-Digital
 2009 Microchip Technology Inc.
bit 1
bit 0
When the AD clock source is selected as 2 T
RC (when ADCS2:ADCS0 = 000 or x11), in
extremely rare cases, the E
Error) and E
exceed the data sheet specification at codes 511
and 512 only.
Work around
Select the AD clock source as 4 T
16 T
2 T
Date Codes that pertain to this issue:
All engineering and production devices.
OSC
OSC
or RC.
, 32 T
Converter
WUE: Wake-up Enable bit
Asynchronous mode:
1 = EUSART will continue to sample the RX pin with the interrupt generated on the falling edge; bit
0 = RX pin is not monitored or rising edge detected
Synchronous mode:
Unused in this mode.
ABDEN: Auto-Baud Detect Enable bit
Asynchronous mode:
1 = Enable baud rate measurement on the next character. Requires reception of a Sync field (55h);
0 = Baud rate measurement disabled or completed
Synchronous mode:
Unused in this mode.
DL
OSC
(Differential Linearity Error) may
cleared in hardware on following rising edge
cleared in hardware upon completion.
BAUDCON: BAUD RATE CONTROL REGISTER (CONTINUED)
or 64 T
OSC
IL
and avoid selecting
(Integral Linearity
OSC
, 8 T
PIC18F2420/2520/4420/4520
OSC
OSC
or
,
5. Module: Enhanced Universal
1.
2.
3.
4.
5.
In rare situations when interrupts are enabled,
unexpected results may occur if:
• The EUSART is disabled (the SPEN bit,
• The EUSART is re-enabled (RCSTA <7> = 1)
• A two-cycle instruction is executed
Work around
Add a 2-T
Disable
PIE1<5>, = 0).
Disable the EUSART (RCSTA <7>, = 0).
Re-enable the EUSART (RCSTA <7> = 1).
Re-enable Receive Interrupts (PIE1<5> = 1).
(This is the first T
Execute an NOP instruction.
(This is the second T
Date Codes that pertain to this issue:
All engineering and production devices.
RCSTA <7>, = 0)
CY
Synchronous Asynchronous
Receiver Transmitter (EUSART)
Receive
delay after re-enabling the EUSART.
CY
delay.)
CY
Interrupts
delay.)
DS80304D-page 3
(RCIE
bit,