PIC18F2431-I/MM Microchip Technology, PIC18F2431-I/MM Datasheet - Page 88
PIC18F2431-I/MM
Manufacturer Part Number
PIC18F2431-I/MM
Description
16 KB Flash, 768 RAM, 22 I/O 28 QFN-S 6x6m TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
Specifications of PIC18F2431-I/MM
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-QFN
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
24
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM183021, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 5 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Request inventory verification / Request inventory verification
Other names
PIC18F2431-I/ML
PIC18F2431-I/ML
PIC18F2431-I/ML
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F2431-I/MM
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC18F2431-I/MM
Manufacturer:
MICROCHI
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- Current page: 88 of 392
- Download datasheet (4Mb)
PIC18F2331/2431/4331/4431
8.2.2
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program
memory and data RAM.
8.2.3
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte
(TBLPTRU:TBLPTRH:TBLPTRL). These three regis-
ters join to form a 22-bit wide pointer. The low-order
21 bits allow the device to address up to 2 Mbytes of
program memory space. Setting the 22nd bit allows
access to the Device ID, the User ID and the
Configuration bits.
The TBLPTR is used by the TBLRD and TBLWT instruc-
tions. These instructions can update the TBLPTR in
one of four ways based on the table operation. These
operations are shown in
on the TBLPTR only affect the low-order 21 bits.
TABLE 8-1:
FIGURE 8-3:
DS39616D-page 88
TBLRD*+
TBLWT*+
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
Example
TBLRD*
TBLWT*
21
TABLAT
TBLPTR
REGISTER
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
TBLPTRU
–
–
TABLE POINTER BOUNDARIES BASED ON OPERATION
TABLE LATCH REGISTER
TABLE POINTER
Table
16
8-1. These operations
15
TABLE ERASE/WRITE
TBLPTR<21:6>
TABLE READ – TBLPTR<21:0>
TBLPTR is incremented before the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented after the read/write
TBLPTRH
Operation on Table Pointer
TBLPTR is not modified
8.2.4
TBLPTR is used in reads, writes and erases of the
Flash program memory.
When a TBLRD is executed, all 22 bits of the Table
Pointer determine which byte is read from program or
configuration memory into TABLAT.
When a TBLWT is executed, the three LSbs of the Table
Pointer (TBLPTR<2:0>) determine which of the eight
program memory holding registers is written to. When
the timed write to program memory (long write) begins,
the 19 MSbs of the Table Pointer, TBLPTR
(TBLPTR<21:3>), will determine which program
memory block of 8 bytes is written to (TBLPTR<2:0>
are ignored). For more detail, see
“Writing to Flash Program
When an erase of program memory is executed, the
16 MSbs of the Table Pointer (TBLPTR<21:6>) point to
the 64-byte block that will be erased. The Least
Significant bits (TBLPTR<5:0>) are ignored.
Figure 8-3
TBLPTR based on Flash program memory operations.
8
7
TABLE POINTER BOUNDARIES
describes the relevant boundaries of
TBLPTRL
2010 Microchip Technology Inc.
TABLE WRITE
TBLPTR<5:0>
Memory”.
Section 8.5
0
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