PIC18F2321-E/SS Microchip Technology, PIC18F2321-E/SS Datasheet - Page 77
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F2321-E/SS
Manufacturer Part Number
PIC18F2321-E/SS
Description
8KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 SSOP .209in TUBE
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(402 pages)
3.PIC18F2221-ISO.pdf
(8 pages)
4.PIC18F2221-ISO.pdf
(30 pages)
5.PIC18F2221-ISO.pdf
(46 pages)
Specifications of PIC18F2321-E/SS
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2321-E/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18F2221-ISO PDF datasheet #5
- Current page: 77 of 402
- Download datasheet (7Mb)
6.5.3
The use of Indexed Literal Offset Addressing mode
effectively changes how the first 96 locations of Access
RAM (00h to 5Fh) are mapped. Rather than containing
just the contents of the bottom half of Bank 0, this mode
maps the contents from Bank 0 and a user-defined
“window” that can be located anywhere in the data
memory space. The value of FSR2 establishes the
lower boundary of the addresses mapped into the
window, while the upper boundary is defined by FSR2
plus 95 (5Fh). Addresses in the Access RAM above
5Fh are mapped as previously described (see
Section 6.3.2 “Access Bank”). An example of Access
Bank remapping in this addressing mode is shown in
Figure 6-9.
FIGURE 6-9:
© 2009 Microchip Technology Inc.
Example Situation:
Locations in the region
from the FSR2 Pointer
(120h) to the pointer plus
05Fh (17Fh) are mapped
to
Access RAM (000h-05Fh).
Locations in Bank 0, from
060h to 07Fh, are mapped
as usual to the middle of
the Access Bank.
Special Function Regis-
ters at F80h through FFFh
are
through FFh, as usual.
Bank 0 addresses below
5Fh can still be addressed
by using the BSR.
ADDWF f, d, a
FSR2H:FSR2L = 120h
the
mapped
MAPPING THE ACCESS BANK IN
INDEXED LITERAL OFFSET
ADDRESSING MODE
bottom
to
of
REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET
ADDRESSING MODE
PIC18F2221/2321/4221/4321 FAMILY
80h
the
FFFh
05Fh
07Fh
17Fh
F00h
F80h
000h
100h
120h
200h
Data Memory
Window
Bank 14
Bank 15
through
Bank 1
Bank 1
Bank 0
Bank 2
Bank 0
SFRs
Remapping of the Access Bank applies only to opera-
tions using the Indexed Literal Offset Addressing
mode. Operations that use the BSR (Access RAM bit is
‘1’) will continue to use direct addressing as before.
6.6
Enabling the extended instruction set adds eight
additional commands to the existing PIC18 instruction
set. These instructions are executed as described in
Section 24.2 “Extended Instruction Set”.
PIC18 Instruction Execution and
the Extended Instruction Set
Bank 1 “Window”
Access Bank
Bank 0
SFRs
DS39689F-page 77
00h
5Fh
7Fh
80h
FFh
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