PIC18F2320-E/SO Microchip Technology, PIC18F2320-E/SO Datasheet - Page 3

• Manufacturer Part Number: PIC18F2320-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. Module: MSSP (SPI, Slave Mode)
7. Module: Data EEPROM
© 2007 Microchip Technology Inc.
In its current implementation, the SS (Slave
Select) control signal generated by an external
master processor may not be successfully recog-
nized by the PIC
Slave Select mode (SSPM3:SSPM0 = 0100). In
particular, it has been observed that faster transi-
tions (those with shorter fall times) are more likely
to be missed than slower transitions.
Work around
Insert a series resistor between the source of the
SS signal and the corresponding SS input line of
the microcontroller. The value of the resistor is
dependent on both the application system’s
characteristics and process variations between
microcontrollers. Experimentation and thorough
testing is encouraged.
This is a recommended solution; others may exist.
Date Codes that pertain to this issue:
All engineering and production devices.
When writing to the data EEPROM, the contents of
the data EEPROM memory may not be written as
expected.
Work around
Either of two work arounds can be used:
1. Before beginning any writes to the data
2. Configure the BOR as enabled (any voltage).
Date Codes that pertain to this issue:
All engineering and production devices.
EEPROM, enable the LVD (any voltage) and
wait for the internal voltage reference to
become stable. LVD interrupt requests may be
ignored. Once the LVD voltage reference is
stable, perform all EEPROM writes normally.
When writes have been completed, the LVD
may be disabled.
Select a threshold below V
operation. If V
the device will be held in BOR Reset.
DD
®
microcontroller operating in
is below the BOR threshold,
DD
to allow normal
PIC18F2220/2320/4220/4320
8. Module: Oscillator Configurations
9. Module: Oscillator Configurations
10. Module: Oscillator Configurations
The INTRC and INTOSC clock sources are both
adjusted using the OSCTUNE register and may
not be adjusted separately. Peripherals that use
the INTRC clock source (WDT and FSCM) also
are affected.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
This revision of silicon does not have the
OSCTUNE 2 register. Address F9Bh is not
implemented.
Work around
If the INTRC frequency is to be adjusted, modify
the contents of the OSCTUNE register.
Date Codes that pertain to this issue:
All engineering and production devices.
The INTOSC clock source requires more start-up
time than what is stated in the data sheet. The
IOFS bit (OSCCON<2>) will indicate the INTOSC
has settled in approximately 4 ms.
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
(OSCTUNE Register)
(OSCTUNE 2 Register)
(INTOSC Clock Source)
DS80187D-page 3