PIC18F2320-E/SO Microchip Technology, PIC18F2320-E/SO Datasheet - Page 11

• Manufacturer Part Number: PIC18F2320-E/SO
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2320-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIGURE 3-2:
FIGURE 3-3:
3.3
Programming code memory is accomplished by first
loading data into the appropriate write buffers and then
initiating a programming sequence. Each panel in the
code memory space (see Figure 2-7 and Figure 2-8)
has an 8-byte deep write buffer that must be loaded
prior to initiating a write sequence. The actual memory
write sequence takes the contents of these buffers and
programs the associated EEPROM code memory.
The programming duration is externally timed and is
controlled by PGC. After a “Start Programming” com-
mand is issued (4-bit command, ‘1111’), a NOP is
issued, where the 4th PGC is held high for the duration
of the programming time, P9 (see Figure 3-6).
 2010 Microchip Technology Inc.
PGC
PGD
4-Bit Command
Code Memory Programming
1
0
2
0
3
1
4
1
Delay P11 + P10
Load Address
Entire Device
P5
Pointer to
BULK ERASE FLOW
Write 80h
BULK ERASE TIMING
3C0004h
to Erase
Done
Time
1
Start
0
Data Payload
2
0
16-Bit
15 16
0
0
P5A
4-Bit Command
1
0
2
0
3
0
4
0
PGD = Input
P5
1
0
2
0
NOP
3.2.1
When using low-voltage ICSP, the part must be
supplied by the voltage specified in parameter D111 if a
Bulk Erase is to be executed. All other Bulk Erase
details as described above apply.
If it is determined that a program memory erase must
be performed at a supply voltage below the Bulk Erase
limit, refer to the erase methodology described in
Section 3.3.1 “Modifying Code Memory”.
If it is determined that a data EEPROM erase must be
performed at a supply voltage below the Bulk Erase
limit, follow the methodology described in Section 3.4
“Data EEPROM Programming” and write zeros to the
array.
After PGC is brought low, the programming sequence
is terminated. PGC must be held low for the time
specified by parameter P10 to allow high-voltage
discharge of the memory array.
The code sequence to program a device is shown in
Table 3-3. The flowchart shown in Figure 3-5 depicts
the logic necessary to completely write a device.
15 16
Note:
0
0
P5A
PIC18FX220/X320
4-Bit Command
1
LOW-VOLTAGE ICSP BULK ERASE
0
The TBLPTR register must contain the
same offset value when initiating the
programming sequence as it did when the
write buffers were loaded.
2
0
3
0
4
0
Erase Time
P11
DS39592F-page 11
P10
Data Payload
16-Bit
1
n
2
n