PIC16HV616T-I/SL Microchip Technology, PIC16HV616T-I/SL Datasheet - Page 8

• Manufacturer Part Number: PIC16HV616T-I/SL
• Description: 1.75KB Flash, 64B RAM, 6 I/O, 8MHz Internal Oscillator 14 SOIC .150in T/R
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16HV616T-I/SL

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 11
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162083 - HEADER MPLAB ICD2 PIC16F616 8/14XLT14SO-1 - SOCKET TRANSITION 14SOIC 150/208
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC12F609/12F615/16F610/16F616/PIC12HV609/12HV615/16HV610/16HV616
4.1.3
The PIC12F609/12F615/16F610/16F616/PIC12HV609/
12HV615/16HV610/16HV616 devices will erase different
memory locations depending on the Program Counter
(PC) and CP. The following sequences can be used to
erase noted memory locations. To erase the program
memory and Configuration Word (0x2007), the following
sequence must be performed. Note the Calibration Word
(0x2008) and User ID (0x2000-0x2003) will not be
erased.
1.
2.
To erase the User ID (0x2000-0x2003), Configuration
Word (0x2007) and program memory, use the following
sequence. Note that the Calibration Word (0x2008) will
not be erased.
1.
2.
3.
TABLE 4-1:
DS41284D-page 8
Load Configuration
Load Data for Program Memory
Read Data from Program Memory
Increment Address
Begin Programming
End Programming
Bulk Erase Program Memory
Do a Bulk Erase Program Memory command.
Wait T
Perform Load Configuration with dummy data to
point the Program Counter (PC) to 0x2000.
Perform a Bulk Erase Program Memory
command.
Wait T
ERA
ERA
ERASE ALGORITHMS
to complete erase.
to complete erase.
Command
COMMAND MAPPING FOR PIC12F609/12F615/16F610/16F616/PIC12HV609/
12HV615/16HV610/16HV616
x
x
x
x
x
x
x
x
x
x
x
1
0
x
Mapping (MSb … LSb)
0
0
0
0
1
1
1
4.1.4
The ICSPCLK pin is used as a clock input and the
ICSPDAT pin is used for entering command bits and
data input/output during serial operation. To input a
command, ICSPCLK is cycled six times. Each
command bit is latched on the falling edge of the clock
with the LSb of the command being input first. The data
input onto the ICSPDAT pin is required to have a mini-
mum setup and hold time (see Table 7-1), with respect
to the falling edge of the clock. Commands that have
data associated with them (Read and Load) are
specified to have a minimum delay of 1 s between the
command and the data. After this delay, the clock pin is
cycled 16 times with the first cycle being a Start bit and
the last cycle being a Stop bit.
During a read operation, the LSb will be transmitted
onto ICSPDAT pin on the rising edge of the second
cycle. For a load operation, the LSb will be latched on
the falling edge of the second cycle. A minimum 1 s
delay is also specified between consecutive com-
mands, except for the End Programming command,
which requires a 100 s T
All commands and data words are transmitted LSb first.
Data is transmitted on the rising edge and latched on
the falling edge of the ICSPCLK. To allow for decoding
of commands and reversal of data pin configuration, a
time separation of at least 1 s is required between a
command and a data word.
The commands that are available are described in
Table 4-1.
0
0
1
1
0
0
0
SERIAL PROGRAM/VERIFY
OPERATION
0
1
0
1
0
1
0
0
0
0
0
0
0
1
 2009 Microchip Technology Inc.
DIS
0, data (14), 0
0, data (14), 0
0, data (14), 0
Externally Timed
Internally Timed
.
Data