PIC16HV610-E/ML Microchip Technology, PIC16HV610-E/ML Datasheet - Page 17
![1.75KB Flash, 64B RAM, 6 I/O, 8MHz Internal Oscillator 16 QFN 4x4mm TUBE](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16HV610-E/ML
Manufacturer Part Number
PIC16HV610-E/ML
Description
1.75KB Flash, 64B RAM, 6 I/O, 8MHz Internal Oscillator 16 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC12F609T-ISN.pdf
(26 pages)
2.PIC16F616T-ISL.pdf
(214 pages)
3.PIC16F616T-ISL.pdf
(8 pages)
4.PIC16HV616-ISL.pdf
(26 pages)
Specifications of PIC16HV610-E/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
11
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-QFN
Processor Series
PIC16H
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS-232 , USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
11
Number Of Timers
2
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162083 - HEADER MPLAB ICD2 PIC16F616 8/14AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFNXLT16QFN1 - SOCKET TRANSITION 14DIP TO 16QFN
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- PIC12F609T-ISN PDF datasheet
- PIC16F616T-ISL PDF datasheet #2
- PIC16F616T-ISL PDF datasheet #3
- PIC16HV616-ISL PDF datasheet #4
- Current page: 17 of 214
- Download datasheet (4Mb)
TABLE 2-2:
© 2009 Microchip Technology Inc.
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
Addr
1:
2:
3:
4:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISC
PCLATH
INTCON
PIE1
PCON
OSCTUNE
ANSEL
PR2
WPUA
IOCA
SRCON0
SRCON1
ADRESL
ADCON1
Name
(3)
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
IRP and RP1 bits are reserved, always maintain these bits clear.
RA3 pull-up is enabled when MCLRE is ‘1’ in the Configuration Word register.
PIC16F616/16HV616 only.
Read-only Register.
—
—
—
—
—
—
—
—
—
—
—
—
(3,4)
(3)
PIC16F610/616/16HV610/616 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter’s (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Module Period Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Least Significant 2 bits of the left shifted result or 8 bits of the right shifted result
SRCS1
RAPU
IRP
ANS7
Bit 7
SR1
GIE
—
—
—
—
—
—
—
—
—
(1)
INTEDG
ADIE
SRCS0
ADCS2
RP1
ANS6
PEIE
Bit 6
SR0
—
—
—
—
—
—
—
(1)
(3)
CCP1IE
TRISA5
TRISC5
WPUA5
C1SEN
ADCS1
IOCA5
ANS5
T0CS
Bit 5
T0IE
RP0
—
—
—
—
PIC16F610/616/16HV610/616
(3)
TRISA4
TRISC4
WPUA4
C2REN
ADCS0
IOCA4
TUN4
ANS4
T0SE
INTE
Bit 4
C2IE
TO
—
—
Write Buffer for upper 5 bits of Program Counter
ANS3
TRISA3
TRISC3
PULSS
IOCA3
TUN3
Bit 3
RAIE
C1IE
PSA
PD
—
—
—
—
(3)
TRISA2
TRISC2
ANS2
WPUA2
PULSR
IOCA2
TUN2
Bit 2
T0IF
PS2
—
—
—
—
Z
(3)
TMR2IE
TRISA1
TRISC1
WPUA1
IOCA1
TUN1
ANS1
INTF
Bit 1
POR
PS1
DC
—
—
—
(3)
SRCLKEN 0000 00-0 69, 117
TRISC0
TMR1IE
WPUA0
TRISA0
IOCA0
TUN0
ANS0
Bit 0
RAIF
BOR
PS0
—
—
C
xxxx xxxx 24, 116
1111 1111 19, 116
0000 0000 24, 116
0001 1xxx 18, 116
xxxx xxxx 24, 116
--11 1111 33, 116
--11 1111 42, 116
---0 0000 24, 116
0000 0000 20, 116
-000 0-00 21, 116
---- --qq 23, 116
---0 0000 31, 117
1111 1111 34, 117
1111 1111 55, 117
--11 -111 35, 117
--00 0000 35, 117
00-- ---- 69, 117
xxxx xxxx 80, 117
-000 ---- 79, 117
POR, BOR
Value on
DS41288F-page 17
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Page
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