PIC16F886-E/SS Microchip Technology, PIC16F886-E/SS Datasheet - Page 197

• Manufacturer Part Number: PIC16F886-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F886-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SSOP
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 368 B
• Interface Type: MSSP, EUSART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM164123, DM164120-3, DV164122
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM164123 - KIT MANAGEMENT SYSTEM PICDEM
• Lead Free Status / Rohs Status: Details

13.4.5
In I
located in the lower 7 bits of the SSPADD register
(Figure 13-11). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is
decremented twice per instruction cycle (T
Q2 and Q4 clocks. In I
reloaded automatically. If clock arbitration is taking
place, for instance, the BRG will be reloaded when the
SCL pin is sampled high (Figure 13-12).
FIGURE 13-11:
FIGURE 13-12:
© 2009 Microchip Technology Inc.
2
C Master mode, the reload value for the BRG is
BAUD RATE GENERATOR
SDA
SCL
BRG
Value
BRG
Reload
BAUD RATE GENERATOR BLOCK DIAGRAM
BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
2
C Master mode, the BRG is
SSPM<3:0>
03h
SCL
DX
SCL de-asserted but slave holds
SCL low (clock arbitration)
02h
SCL is sampled high, reload takes
place and BRG starts its count
SSPM<3:0>
CY
) on the
Control
Reload
PIC16F882/883/884/886/887
01h
CLKOUT
BRG decrements on
Q2 and Q4 cycles
00h (hold off)
Reload
DX-1
BRG Down Counter
SSPADD<6:0>
SCL allowed to transition high
03h
F
OSC
02h
/4
DS41291F-page 195