PIC16F873-04E/SO Microchip Technology, PIC16F873-04E/SO Datasheet - Page 70
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PIC16F873-04E/SO
Manufacturer Part Number
PIC16F873-04E/SO
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F688T-ISL.pdf
(688 pages)
3.PIC16F873-04SO.pdf
(218 pages)
4.PIC16F873-04SO.pdf
(5 pages)
5.PIC16F873-04SO.pdf
(5 pages)
6.PIC16F873-04SO.pdf
(4 pages)
Specifications of PIC16F873-04E/SO
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
7KB (4K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
192 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16F87304E/SO
- PIC16F616T-ISL PDF datasheet
- PIC16F688T-ISL PDF datasheet #2
- PIC16F873-04SO PDF datasheet #3
- PIC16F873-04SO PDF datasheet #4
- PIC16F873-04SO PDF datasheet #5
- PIC16F873-04SO PDF datasheet #6
- Current page: 70 of 218
- Download datasheet (4Mb)
PIC16F87X
REGISTER 9-3:
DS30292C-page 68
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 91h)
bit 7
GCEN: General Call Enable bit (In I
1 = Enable interrupt when a general call address (0000h) is received in the SSPSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (In I
In Master Transmit mode:
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT: Acknowledge Data bit (In I
In Master Receive mode:
Value that will be transmitted when the user initiates an Acknowledge sequence at the
end of a receive.
1 = Not Acknowledge
0 = Acknowledge
ACKEN: Acknowledge Sequence Enable bit (In I
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit.
0 = Acknowledge sequence idle
RCEN: Receive Enable bit (In I
1 = Enables Receive mode for I
0 = Receive idle
SCK Release Control:
1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware.
0 = STOP condition idle
1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = Repeated START condition idle
1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware.
0 = START condition idle
Legend:
R = Readable bit
- n = Value at POR
Note:
PEN: STOP Condition Enable bit (In I
RSEN: Repeated START Condition Enable bit (In I
SEN: START Condition Enable bit (In I
GCEN
R/W-0
Automatically cleared by hardware.
For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
mode, this bit may not be set (no spooling), and the SSPBUF may not be written (or
writes to the SSPBUF are disabled).
ACKSTAT
R/W-0
ACKDT
R/W-0
W = Writable bit
’1’ = Bit is set
2
2
C Master mode only)
C
2
2
C Master mode only)
C Slave mode only)
ACKEN
2
R/W-0
C Master mode only)
2
2
C Master mode only)
C Master mode only)
2
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
C Master mode only)
R/W-0
RCEN
2
C Master mode only)
R/W-0
PEN
2
C module is not in the IDLE
2001 Microchip Technology Inc.
x = Bit is unknown
R/W-0
RSEN
R/W-0
SEN
bit 0
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