PIC16F870-E/SO Microchip Technology, PIC16F870-E/SO Datasheet - Page 52

• Manufacturer Part Number: PIC16F870-E/SO
• Description: 28 PIN, 3.5KB ENH FLASH, 128 RAM, 22 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F870-E/SO

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB16F871 - BOARD DAUGHTER ICEPIC3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F870/871
6.1
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
(T1CON<2>), has no effect, since the internal clock is
always in sync.
FIGURE 6-1:
6.3
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RC1/T1OSI, when bit T1OSCEN is
set, or on pin RC0/T1OSO/T1CKI, when bit T1OSCEN
is cleared.
FIGURE 6-2:
DS30569B-page 50
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
RC0/T1OSO/T1CKI
Timer1 Operation in Timer Mode
Timer1 Operation in Synchronized
Counter Mode
OSC
/4. The synchronize control bit, T1SYNC
RC1/T1OSI
Set Flag bit
TMR1IF on
Overflow
TIMER1 INCREMENTING EDGE
TIMER1 BLOCK DIAGRAM
TMR1H
T1OSC
TMR1
TMR1L
Oscillator
T1OSCEN
Enable
(1)
Clock
F
Internal
OSC
/4
TMR1ON
6.2
Timer1 may operate in either a Synchronous, or an
Asynchronous mode, depending on the setting of the
TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler, however, will continue to increment.
On/Off
TMR1CS
1
0
Timer1 Counter Operation
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
0
1
2
 2003 Microchip Technology Inc.
Synchronized
Clock Input
Synchronize
Q Clock
det