PIC16F716-E/SS Microchip Technology, PIC16F716-E/SS Datasheet - Page 62

• Manufacturer Part Number: PIC16F716-E/SS
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F716-E/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB16F716 - BOARD DAUGHTER ICEPIC3AC162054 - HEADER INTERFACE ICD2 16F716
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F716
REGISTER 8-3:
TABLE 8-6:
DS41206B-page 60
CCPR1L
CCPR1H
CCP1CON
ECCPAS
INTCON
PIE1
PIR1
PR2
PWM1CON
TMR1L
TMR1H
TMR2
TRISB
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6-0
Name
PRSEN
R/W-0
Capture/Compare/PWM Register 1 (LSB)
Capture/Compare/PWM Register 1 (MSB)
Timer2 Period Register
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
Timer2 Module’s Register
ECCPASE
PRSEN
TRISB7
P1M1
Bit 7
GIE
—
—
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
PDC<6:0>: PWM Delay Count bits
PDCn = Number of F
REGISTERS ASSOCIATED WITH PWM
R/W-0
PDC6
away; the PWM restarts automatically
ECCPAS2
PWM1CON: ENHANCED PWM CONTROL REGISTER
TRISB6
PDC6
P1M0
Bit 6
ADIE
PEIE
ADIF
should transition active and the actual time it transitions active
W = Writable bit
‘1’ = Bit is set
TRISB5
DC1B1
PDC5
R/W-0
Bit 5
PDC5
T0IE
—
—
—
OSC
ECCPAS0
/4 (4 * T
TRISB4
DC1B0
PDC4
Bit 4
INTE
—
—
R/W-0
PDC4
OSC
CCP1M3
PSSAC1
TRISB3
PDC3
) cycles between the scheduled time when a PWM signal
Bit 3
RBIE
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
PDC3
CCP1M2
PSSAC0
CCP1IE
CCP1IF
TRISB2
PDC2
Bit 2
T0IF
CCP1M1
PSSBD1
TMR2IE
TMR2IF
TRISB1
PDC1
Bit 1
INTF
R/W-0
PDC2
CCP1M0
PSSBD0
TMR1IE
TMR1IF
TRISB0
PDC0
Bit 0
RBIF
© 2007 Microchip Technology Inc.
x = Bit is unknown
R/W-0
PDC1
POR, BOR
xxxx xxxx
xxxx xxxx
0000 0000
00-0 0000
0000 000x
-0-- -000
-0-- 0000
1111 1111
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
1111 1111
Value on
R/W-0
xxxx xxxx
xxxx xxxx
0000 0000
00-0 0000
0000 000x
-0-- -000
-0-- -000
1111 1111
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
1111 1111
PDC0
Value on
all other
Resets
bit 0