PIC16F676-I/ML Microchip Technology, PIC16F676-I/ML Datasheet - Page 22
![1.75 KB Flash, 64 RAM, 12 I/O 16 QFN 4x4mm TUBE](/photos/6/65/66536/mfg_mcp7386x_qfn_sml.jpg)
PIC16F676-I/ML
Manufacturer Part Number
PIC16F676-I/ML
Description
1.75 KB Flash, 64 RAM, 12 I/O 16 QFN 4x4mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC12F629T-ISN.pdf
(24 pages)
3.PIC16F630-ISL.pdf
(132 pages)
4.PIC16F630-ISL.pdf
(2 pages)
5.PIC16F630-ISL.pdf
(10 pages)
Specifications of PIC16F676-I/ML
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
12
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
16-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164324 - MODULE SKT FOR MPLAB 8DFN/16QFN
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F676-I/ML
Manufacturer:
MICROCHIP
Quantity:
4 500
PIC16F630/676
REGISTER 3-2:
REGISTER 3-3:
3.2.2
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits IOCAx enable
or disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set, the PORTA Change Interrupt flag
bit (RAIF) in the INTCON register.
DS40039F-page 22
bit 7-6:
bit 5-0:
bit 7-6
bit 5-4
bit 3
bit 2-0
INTERRUPT-ON-CHANGE
TRISA — PORTA TRI-STATE REGISTER (ADDRESS: 85h)
WPUA — WEAK PULL-UP REGISTER (ADDRESS: 95h)
bit 7
bit 7
Unimplemented: Read as ‘0’
TRISA<5:0>: PORTA Tri-State Control bits
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
Legend:
R = Readable bit
- n = Value at POR
Unimplemented: Read as ‘0’
WPUA<5:4>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
WPUA<2:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global RAPU must be enabled for individual pull-ups to be enabled.
Legend:
R = Readable bit
- n = Value at POR
Note:
U-0
U-0
—
—
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISA = 0).
TRISA<3> always reads 1.
U-0
U-0
—
—
TRISA5
WPUA5
R/W-x
R/W-1
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
TRISA4
WPUA4
R/W-x
R/W-1
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared.
Note:
Any read or write of PORTA. This will end the
mismatch condition.
Clear the flag bit RAIF.
TRISA3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U-0
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
—
R-1
WPUA2
R/W-1
TRISA2
R/W-x
2010 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
WPUA1
R/W-1
TRISA1
R/W-x
WPUA0
TRISA0
R/W-1
R/W-x
bit 0
bit 0