PIC16CE623-04I/P Microchip Technology, PIC16CE623-04I/P Datasheet - Page 20

• Manufacturer Part Number: PIC16CE623-04I/P
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,18PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16CE623-04I/P

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Size: 896B (512 x 14)
• Program Memory Type: OTP
• Eeprom Size: 128 x 8
• Ram Size: 96 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 96 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 309-1059 - ADAPTER 18 ZIF BD W/18SO PLUGSDVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

situations for the loading of the PC. The upper example in
PIC16CE62X
4.3
The program counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-6 shows the two
the figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0>
shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3>
FIGURE 4-6:
4.3.1
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note, “Implementing a Table Read"
(AN556).
DS40182C-page 20
PC
PC
12
12 11 10
2
PCL and PCLATH
COMPUTED GOTO
5
PCH
PCLATH<4:3>
PCH
PCLATH
PCLATH<4:0>
8
PCLATH
8
PCH). The lower example in the figure
LOADING OF PC IN
DIFFERENT SITUATIONS
7
7
PCL
PCL
PCH).
11
8
0
0
Instruction with
PCL as
Destination
ALU result
GOTO, CALL
Opcode <10:0>
4.3.2
The PIC16CE62X family has an 8 level deep x 13-bit
wide hardware stack (Figure 4-2 and Figure 4-3). The
stack space is not part of either program or data
space and the stack pointer is not readable or writ-
able. The PC is PUSHed onto the stack when a CALL
instruction is executed or an interrupt causes a
branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1:
Note 2:
STACK
There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
There are no instruction/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or the vectoring to an
interrupt address.
1999 Microchip Technology Inc.