PIC16C773/SS Microchip Technology, PIC16C773/SS Datasheet - Page 63

• Manufacturer Part Number: PIC16C773/SS
• Description: 28 PIN, 7KB OTP, 256 RAM, 22 I/O,
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C773/SS

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 6x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 309-1025 - ADAPTER 28-SSOP TO 28-DIP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2
The MSSP module in I
master and slave functions (including general call sup-
port) and provides interrupts on start and stop bits in
hardware to determine a free bus (multi-master func-
tion). The MSSP module implements the standard
mode specifications as well as 7-bit and 10-bit address-
ing.
Refer to Application Note AN578, "Use of the SSP
Module in the I
A "glitch" filter is on the SCL and SDA pins when the pin
is an input. This filter operates in both the 100 kHz and
400 kHz modes. In the 100 kHz mode, when these pins
are an output, there is a slew rate control of the pin that
is independant of device frequency.
FIGURE 8-10: I
1999 Microchip Technology Inc.
SDA
SCL
MSSP I
2
Read
clock
C Multi-Master Environment."
shift
2
DIAGRAM
2
C Operation
C SLAVE MODE BLOCK
MSb
Stop bit detect
SSPBUF reg
Match detect
SSPADD reg
2
SSPSR reg
Start and
C mode fully implements all
LSb
Write
(SSPSTAT reg)
data bus
Internal
Set, Reset
S, P bits
Addr Match
Advance Information
FIGURE 8-11: I
Two pins are used for data transfer. These are the SCL
pin, which is the clock, and the SDA pin, which is the
data. The SDA and SCL pins that are automatically
configured when the I
module functions are enabled by setting SSP Enable
bit SSPEN (SSPCON<5>).
The MSSP module has six registers for I
They are the:
• SSP Control Register (SSPCON)
• SSP Control Register2 (SSPCON2)
• SSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer (SSPBUF)
• SSP Shift Register (SSPSR) - Not directly acces-
• SSP Address Register (SSPADD)
The SSPCON register allows control of the I
tion. Four mode selection bits (SSPCON<3:0>) allow
one of the following I
• I
• I
• I
Before selecting any I
must be programmed to inputs by setting the appropri-
ate TRIS bits. Selecting an I
SSPEN bit, enables the SCL and SDA pins to be used
as the clock and data lines in I
sible
SDA
SCL
Baud Rate Generator
2
2
2
SSPADD<6:0>
C Slave mode (7-bit address)
C Slave mode (10-bit address)
C Master mode, clock = OSC/4 (SSPADD +1)
7
Read
clock
shift
DIAGRAM
2
C MASTER MODE BLOCK
MSb
2
Start and Stop bit
2
detect / generate
C modes to be selected:
2
C mode, the SCL and SDA pins
Match detect
SSPADD reg
C mode is enabled. The SSP
SSPBUF reg
SSPSR reg
PIC16C77X
2
2
C mode, by setting the
C mode.
LSb
DS30275A-page 63
Write
(SSPSTAT reg)
and Set SSPIF
Set/Clear S bit
Clear/Set P bit
data bus
2
Internal
C operation.
Addr Match
and
2
C opera-