PIC16C717-I/SS Microchip Technology, PIC16C717-I/SS Datasheet - Page 96
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16C717-I/SS
Manufacturer Part Number
PIC16C717-I/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,20PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16C770-ISO.pdf
(220 pages)
3.PIC16C770-ISO.pdf
(6 pages)
4.PIC16C770-ISO.pdf
(8 pages)
Specifications of PIC16C717-I/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
309-1016 - ADAPTER 20-SSOP TO 18-DIP
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16C717I/SS
- PIC16F818-ISO PDF datasheet
- PIC16C770-ISO PDF datasheet #2
- PIC16C770-ISO PDF datasheet #3
- PIC16C770-ISO PDF datasheet #4
- Current page: 96 of 220
- Download datasheet (4Mb)
PIC16C717/770/771
9.2.17
Multi-master mode support is achieved by bus arbitra-
tion. When the master outputs address/data bits onto
the SDA pin, bus arbitration is initiated when one mas-
ter outputs a ’1’ on SDA (by letting SDA float high) and
another master asserts a ’0’. If the expected data on
SDA is a ’1’ and the data sampled on the SDA pin = ’0’,
then a bus collision has taken place. The master that
expected a ‘1’ will set the Bus Collision Interrupt Flag,
BCLIF, and reset the I
(Figure 9-23).
A bus collision during transmit results in the following
events:
• The transmission is halted.
• The BF flag is cleared
• The SDA and SCL lines are de-asserted
• The restriction on writing to the SSPBUF during
When the user services the bus collision interrupt ser-
vice routine, and if the I
resume communication by asserting a START condi-
tion.
FIGURE 9-23:
DS41120B-page 94
transmission is lifted.
SDA
SCL
BCLIF
MULTI -MASTER
COMMUNICATION, BUS
COLLISION, AND BUS
ARBITRATION
BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE
2
2
C bus is free, the user can
C port to its IDLE state.
Data changes
while SCL = 0
Advance Information
SDA released
by master
SDA line pulled low
by another source
A bus collision during a START, Repeated START,
STOP or Acknowledge condition results in the following
events:
• The condition is aborted.
• The SDA and SCL lines are de-asserted.
• The respective control bits in the SSPCON2 regis-
When the user services the bus collision interrupt ser-
vice routine, and if the I
resume communication by asserting a START condi-
tion.
The Master will continue to monitor the SDA and SCL
pins, and if a STOP condition occurs, the SSPIF bit will
be set.
A write to the SSPBUF will start the transmission of
data at the first data bit, regardless of where the trans-
mitter left off when bus collision occurred.
In Multi-Master mode, the interrupt generation on the
detection of START and STOP conditions allows the
determination of when the bus is free. Control of the I
bus can be taken when the P bit is set in the SSPSTAT
register, or the bus is idle and the S and P bits are
cleared.
ter are cleared.
Sample SDA. While SCL is high
data doesn’t match what is driven
by the master.
Bus collision has occurred.
Set bus collision
interrupt.
2
C bus is free, the user can
2002 Microchip Technology Inc.
2
C
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