PIC16C62B-04/SS Microchip Technology, PIC16C62B-04/SS Datasheet - Page 100
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PIC16C62B-04/SS
Manufacturer Part Number
PIC16C62B-04/SS
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,SSOP,28PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheets
1.PIC16F818-ISO.pdf
(6 pages)
2.PIC16C62B-04SO.pdf
(120 pages)
3.PIC16C62B-04SO.pdf
(5 pages)
Specifications of PIC16C62B-04/SS
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
28-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164307 - MODULE SKT FOR PM3 28SSOP309-1025 - ADAPTER 28-SSOP TO 28-DIPXLT28SS-1 - SOCKET TRANSITION ICE 28SSOP
Eeprom Size
-
Data Converters
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16C62B-04/SS
Manufacturer:
MIC
Quantity:
240
Part Number:
PIC16C62B-04/SS
Manufacturer:
MICR
Quantity:
20 000
PIC16C62B/72A
FIGURE 13-16: I
TABLE 13-12: I
DS35008B-page 100
100*
101*
102*
103*
90*
91*
106*
107*
92*
109*
110*
Note 1:
Param.
No.
*
2: A fast-mode (400 kHz) I
These parameters are characterized but not tested.
SDA
Out
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the fall-
ing edge of SCL to avoid unintended generation of START or STOP conditions.
250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line T
max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I
SDA
In
SCL
Note:
T
T
T
T
T
T
T
T
T
T
T
Cb
R
AA
HIGH
LOW
F
SU
HD
HD
SU
SU
BUF
Sym
:
:
:
:
:
STA
DAT
STO
STA
DAT
2
2
C BUS DATA TIMING
C BUS DATA REQUIREMENTS
Refer to Figure 13-4 for load conditions.
Clock high time
Clock low time
SDA and SCL rise
time
SDA and SCL fall
time
START condition
setup time
START condition hold
time
Data input hold time
Data input setup time
STOP condition setup
time
Output valid from
clock
Bus free time
Bus capacitive loading
90
103
91
2
C-bus device can be used in a standard-mode (100 kHz) I
109
Characteristic
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
SSP Module
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100 kHz mode
400 kHz mode
100
Preliminary
106
101
109
20 + 0.1Cb
20 + 0.1Cb
107
1.5T
1.5T
Min
250
100
4.0
0.6
4.7
1.3
4.7
0.6
4.0
0.6
4.7
0.6
4.7
1.3
—
—
—
—
—
0
0
CY
CY
2
C bus specification) before the SCL line is released.
1000
3500
Max
300
300
300
0.9
400
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
C-bus system, but the requirement Tsu:DAT
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
s
s
s
s
s
s
s
s
s
s
s
s
s
1998 Microchip Technology Inc.
92
Conditions
Device must operate at a min-
imum of 1.5 MHz
Device must operate at a min-
imum of 10 MHz
Device must operate at a min-
imum of 1.5 MHz
Device must operate at a min-
imum of 10 MHz
Cb is specified to be from
10-400 pF
Cb is specified to be from
10-400 pF
Only relevant for repeated
START condition
After this period the first clock
pulse is generated
Note 2
Note 1
Time the bus must be free
before a new transmission
can start
102
110
R