PC16550DN National Semiconductor, PC16550DN Datasheet - Page 18

• Manufacturer Part Number: PC16550DN
• Description: UART IC
• Manufacturer: National Semiconductor

Specifications of PC16550DN

• Transceiver Type: RS232
• Mounting Type: Through Hole
• Peak Reflow Compatible (260 C): No
• Ic Function: UART IC
• Supply Voltage: 5V
• No. Of Transceivers: 1
• Data Rate Max: 128Kbps
• Leaded Process Compatible: No
• Supply Current: 15mA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8 0 Registers
When the CPU accesses the IIR the UART freezes all inter-
rupts and indicates the highest priority pending interrupt to
the CPU While this CPU access is occurring the UART
records new interrupts but does not change its current indi-
cation until the access is complete Table II shows the con-
tents of the IIR Details on each bit follow
Bit 0 This bit can be used in a prioritized interrupt environ-
ment to indicate whether an interrupt is pending When bit 0
is a logic 0 an interrupt is pending and the IIR contents may
be used as a pointer to the appropriate interrupt service
routine When bit 0 is a logic 1 no interrupt is pending
Bits 1 and 2 These two bits of the IIR are used to identify
the highest priority interrupt pending as indicated in Table
IV
Bit 3 In the 16450 Mode this bit is 0 In the FIFO mode this
bit is set along with bit 2 when a timeout interrupt is pending
Bits 4 and 5 These two bits of the IIR are always logic 0
Bits 6 and 7 These two bits are set when FCR0
8 7 INTERRUPT ENABLE REGISTER
This register enables the five types of UART interrupts
Each interrupt can individually activate the interrupt (INTR)
output signal It is possible to totally disable the interrupt
system by resetting bits 0 through 3 of the Interrupt Enable
Register (IER) Similarly setting bits of the IER register to a
logic 1 enables the selected interrupt(s) Disabling an inter-
rupt prevents it from being indicated as active in the IIR and
from activating the INTR output signal All other system
functions operate in their normal manner including the set-
ting of the Line Status and MODEM Status Registers Table
II shows the contents of the IER Details on each bit follow
Bit 0 This bit enables the Received Data Available Interrupt
(and timeout interrupts in the FIFO mode) when set to logic
1
Bit 1 This bit enables the Transmitter Holding Register
Empty Interrupt when set to logic 1
Bit 2 This bit enables the Receiver Line Status Interrupt
when set to logic 1
Bit 3 This bit enables the MODEM Status Interrupt when
set to logic 1
Bits 4 through 7 These four bits are always logic 0
8 8 MODEM CONTROL REGISTER
This register controls the interface with the MODEM or data
set (or a peripheral device emulating a MODEM) The con-
tents of the MODEM Control Register are indicated in Table
II and are described below
Bit 0 This bit controls the Data Terminal Ready (DTR) out-
put When bit 0 is set to a logic 1 the DTR output is forced
to a logic 0 When bit 0 is reset to a logic 0 the DTR output
is forced to a logic 1
Note The DTR output of the UART may be applied to an EIA inverting line
Bit 1 This bit controls the Request to Send (RTS) output
Bit 1 affects the RTS output in a manner identical to that
described above for bit 0
Bit 2 This bit controls the Output 1 (OUT 1) signal which is
an auxiliary user-designated output Bit 2 affects the OUT 1
output in a manner identical to that described above for bit
0
driver (such as the DS1488) to obtain the proper polarity input at the
succeeding MODEM or data set
(Continued)
e
1
18
Bit 3 This bit controls the Output 2 (OUT 2) signal which is
an auxiliary user-designated output Bit 3 affects the OUT 2
output in a manner identical to that described above for bit
0
Bit 4 This bit provides a local loopback feature for diagnos-
tic testing of the UART When bit 4 is set to logic 1 the
following occur the transmitter Serial Output (SOUT) is set
to the Marking (logic 1) state the receiver Serial Input (SIN)
is disconnected the output of the Transmitter Shift Register
is ‘‘looped back’’ into the Receiver Shift Register input the
four MODEM Control inputs (DSR CTS RI and DCD) are
disconnected and the four MODEM Control outputs (DTR
RTS OUT 1 and OUT 2) are internally connected to the
four MODEM Control inputs and the MODEM Control out-
put pins are forced to their inactive state (high) In the loop-
back mode data that is transmitted is immediately received
This feature allows the processor to verify the transmit-and
received-data paths of the UART
In the loopback mode the receiver and transmitter inter-
rupts are fully operational Their sources are external to the
part The MODEM Control Interrupts are also operational
but the interrupts’ sources are now the lower four bits of the
MODEM Control Register instead of the four MODEM Con-
trol inputs The interrupts are still controlled by the Interrupt
Enable Register
Bits 5 through 7 These bits are permanently set to logic 0
8 9 MODEM STATUS REGISTER
This register provides the current state of the control lines
from the MODEM (or peripheral device) to the CPU In addi-
tion to this current-state information four bits of the MO-
DEM Status Register provide change information These
bits are set to a logic 1 whenever a control input from the
MODEM changes state They are reset to logic 0 whenever
the CPU reads the MODEM Status Register
The contents of the MODEM Status Register are indicated
in Table II and described below
Bit 0 This bit is the Delta Clear to Send (DCTS) indicator
Bit 0 indicates that the CTS input to the chip has changed
state since the last time it was read by the CPU
Bit 1 This bit is the Delta Data Set Ready (DDSR) indicator
Bit 1 indicates that the DSR input to the chip has changed
state since the last time it was read by the CPU
Bit 2 This bit is the Trailing Edge of Ring Indicator (TERI)
detector Bit 2 indicates that the RI input to the chip has
changed from a low to a high state
Bit 3 This bit is the Delta Data Carrier Detect (DDCD) indi-
cator Bit 3 indicates that the DCD input to the chip has
changed state
Note Whenever bit 0 1 2 or 3 is set to logic 1 a MODEM Status Interrupt
Bit 4 This bit is the complement of the Clear to Send (CTS)
input If bit 4 (loop) of the MCR is set to a 1 this bit is
equivalent to RTS in the MCR
Bit 5 This bit is the complement of the Data Set Ready
(DSR) input If bit 4 of the MCR is set to a 1 this bit is
equivalent to DTR in the MCR
Bit 6 This bit is the complement of the Ring Indicator (RI)
input If bit 4 of the MCR is set to a 1 this bit is equivalent to
OUT 1 in the MCR
is generated