MCP6S91-E/P Microchip Technology, MCP6S91-E/P Datasheet

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... These specifications support single- supply applications needing flexible performance or multiple inputs. The one-channel MCP6S91 and the two-channel MCP6S92 are available in 8-pin PDIP, SOIC and MSOP packages. The two-channel MCP6S93 is available in a 10-pin MSOP package. All parts are fully specified from -40° ...

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... SS are not tested in production; they are set by design and characterization. = 0.3V). Both I and I OUT Q MCP6S91/2/3 Function Analog Output External Reference Pin Negative Power Supply SPI Chip Select SPI Serial Data Input SPI Serial Data Output ...

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... PSRR spec describes PSRR+ only pin be tied directly to ground to avoid noise problems. SS are not tested in production; they are set by design and characterization. = 0.3V). Both I and I OUT Q Q_SHDN MCP6S91/2/3 = GND V/V, SS REF SS Conditions (Note -40°C to +125°C (Note ...

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... V/µs E — 4.5 — µV ni — 30 — e — 10 — nV kHz (Note — 4 — fA kHz ni versus G data. ni MCP6S91/2/3 = GND V/V, SS REF SS Conditions All gains; V < 100 mV (Note 1) OUT P-P All gains; V < 100 mV OUT P 1.5V ± 1 5.0V, OUT kHz 1.5V ...

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... SOZ t — 1.5 — — 1 — — 3 — 1.5 — OFF 80 ns), data input set-up time (t 40 ns), SCK high time ( therefore 5.8 MHz. MCP6S91/2/3 = GND V/V, SS REF SS Conditions V µA V µA In Shutdown mode 2.1 mA -400 µ All digital I/O pins µs (Note 1) ...

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... Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-MSOP Thermal Resistance, 10L-MSOP Note 1: Operation in this range must not cause T  2004 Microchip Technology Inc. MCP6S91/2/3 = +2.5V to +5.5V GND Sym Min Typ Max T -40 — ...

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... FIGURE 1-4: Detailed SPI™ Serial Interface Timing; SPI 0,0 Mode.  2004 Microchip Technology Inc OUT FIGURE 1-3: Diagram. t OFF Hi 1/f SCK t DO MCP6S91/2 1.5V 0.3V Gain Select Timing t CSH SCCS CS1 CS0 t SOZ DS21908A-page 7 ...

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... Figure 1-6 shows the relationship between DD the gain and offset specifications referred to in the electrical specifications as follows: EQUATION 1- The DC Gain Drift ( G/ T pin is tied to REF change following equation: EQUATION 1-4: shown in O_LIN  + 0.3V  OS MCP6S91/2/3 t CSH SCCS CS1 CS0 t SOZ = 0.3V and O_ID V – ------------------------------------- - g = 100 – ...

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... REF DD modified for these conditions. The ideal V becomes EQUATION 1- The complete linear model is: V (V) EQUATION 1- ON_LIN = 0V. where the new V EQUATION 1-9: V IN_H The equations for extracting the specifications do not change ( MCP6S91/2/3 CONDITIONS REF = REF DD equation OUT = – V O_ID REF IN REF REF – ...

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... FIGURE 2-5: -10 R -20 -30 -40 -50 -60 -70 -80 -90 -100 1.E+05 100k FIGURE 2-6: (circuit in Figure 6-4). MCP6S91/2/3 = GND V/V, SS REF SS = -40 to +125° Gain Drift (%/°C) DC Gain Drift + -40 to +125° Gain Drift (%/°C) DC Gain Drift +32 V/V CH0 selected R ...

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... FIGURE 2-11: V Voltage. REF 10000 100000 10k 100k FIGURE 2-12: vs. Gain. MCP6S91/2/3 = GND V/V, SS REF SS 600 Samples T = -40 to +125° Input Offset Voltage Drift (µV/°C) Input Offset Voltage Drift REF ...

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... FIGURE 2-17: Voltage. 25% 39 Samples V 20% CH0 = V 15% = 2.5V 10 100 125 FIGURE 2-18: Shutdown Mode. MCP6S91/2/3 = GND V/V, SS REF 2.5V DD Input Referred V = 5.5V DD 100 1000 10000 100000 1000000 ...

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... FIGURE 2-22: vs. Supply Voltage 0.3V DD 0.1 0.01 0.001 5.0 5.5 FIGURE 2-23: Output Swing 2. 0.1 1.E+05 100k 10 FIGURE 2-24: Frequency. MCP6S91/2/3 = GND V/V, SS REF +125° +85° +25° -40°C A Power Supply Voltage (V) Output Short Circuit Current /G: ONL ...

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... FIGURE 2-30: Frequency, V MCP6S91/2/3 = GND V/V, SS REF + 100 1000 Capacitive Load (pF) Gain Peaking vs. Capacitive 5. V/V V OUT Time (1 µs/div) The MCP6S91/2/3 family Measurement kHz OUT 1.E+03 1.E+04 1.E+05 1k 10k 100k Frequency (Hz) THD plus Noise vs OUT P-P DS21908A-page 14 ...

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... FIGURE 2-35: 90% 15 80% 10 70% 60% 5 50% CS 40% 0 30% -5 20% 10% -10 0% -15 1.E+01 1.E+01 1.E+01 FIGURE 2-36: Voltage (register data still valid). MCP6S91/2/3 = GND V/V, SS REF SS 7 5.0V DD 6.5 5.5 4 3.5 2.5 1.5 V OUT 0 -0 +32 -1.5 -2.5 0.5 1 ...

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... 0.2 T 0.1 0.0 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FIGURE 2-39: Input Voltage, V 100 125 MCP6S91/2/3 = GND V/V, SS REF +85°C = +25°C = -40°C A Input Voltage (V) Input Offset Voltage vs. = 5.5V. DD DS21908A-page 16 ...

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... The MCP6S93 device has a SPI interface Serial Output (SO) pin. This is a CMOS push-pull output and does not ever go High-Z. Once the device is deselected (CS goes high forced low. This feature supports daisy-chaining, as explained in Section 5.3 “Daisy- Chain Configuration”. MCP6S91/2/3 and 2. ...

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... PGA Block Diagram. 4.1 Input MUX The MCP6S91 has one input, while the MCP6S92 and MCP6S93 have two inputs (see Figure 4-1). For the lowest input current, float unused inputs. Tying these pins to a voltage near the active channel’s bias voltage also works well ...

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... /2. REF DD 4.2.4 INPUT VOLTAGE AND PHASE REVERSAL The MCP6S91/2/3 amplifier family is designed with CMOS input devices designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-29 shows an exceeding both supplies with no resulting phase inversion. ...

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... The resistive ladder is always connected between V and V ; even in shutdown. This means that the REF OUT output resistance will be on the order with a path for output signals to appear at the input.  2004 Microchip Technology Inc. pin must be – 0.3V and SS is REF ). Staying within MCP6S91/2/3 DS21908A-page 20 ...

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... SO goes low after CS goes high; it has a push-pull output that does not go into a high-Z state. The MCP6S91/2/3 devices operate in SPI modes 0,0 and 1,1. In 0,0 mode, the clock idles in the low state (Figure 5-1). In 1,1 mode, the clock idles in the high state (Figure 5-2) ...

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... NOP or Shutdown, is sent and CS is raised. W-0 U-x U-x U-x M0 — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared MCP6S91/2 the inter- DD DD_VAL pin provides additional transient DD U-x W-0 — A0 bit Bit is unknown ...

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... Gain of +32 Legend Readable bit -n = Value at POR  2004 Microchip Technology Inc. U-x U-x U-x W-0 — — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared MCP6S91/2/3 W-0 W bit Bit is unknown DS21908A-page 23 ...

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... Microchip Technology Inc. U-x U-x U-x U-x — — — — MCP6S92 MCP6S93 CH0 CH0 CH1 CH1 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared MCP6S91/2/3 U-x W-0 — C0 bit Bit is unknown DS21908A-page 24 ...

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... MCP6S91/2/3 The example in Figure 5-3 shows a daisy-chain configuration with two devices, although any number of devices can be configured this way. The MCP6S91 and MCP6S92 can only be used at the far end of the daisy- chain, because they do not have a serial data out (SO) pin. As shown in Figure 5-4 and Figure 5-5, both SI and SO data are sent in 16-bit (2 byte) words ...

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... Instruction Byte for Device 2 SO (first 16 bits out are always zeros) FIGURE 5-5: Serial Bus Sequence for Daisy-Chain Configuration; SPI™ 1,1 Mode.  2004 Microchip Technology Inc. MCP6S91/2 10111213141516 Data Byte Instruction Byte for Device 1 for Device 2 Instruction Byte for Device 2 ...

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... Reference Voltage. 6.2 Capacitive Load and Stability Large capacitive loads can cause stability problems and reduced bandwidth for the MCP6S91/2/3 family of PGAs (Figure 2-26 and Figure 2-28). As the load capacitance increases, there is a corresponding increase in frequency response peaking and step response overshoot and ringing. This happens because a large load capacitance decreases the internal amplifier’ ...

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... Microchip Technology Inc. 6.3.4 SIGNAL COUPLING The input pins of the MCP6S91/2/3 family of PGAs are high-impedance. This makes them especially suscepti- ble to capacitively-coupled noise. Using a ground plane helps reduce this problem. When noise is capacitively coupled, the ground plane provides additional shunt capacitance to ground ...

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... FIGURE 6-5: Wide Dynamic Range Current Measurement Circuit. 6.4.2 SHIFTED GAIN RANGE PGA Figure 6-6 shows a circuit using a MCP6291 at a gain of +10 in front of a MCP6S91. This shifts the overall gain range to +10 V/V to +320 V/V (from +1 V/V to +32 V/V MCP6291 MCP6S91 10 ...

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... The low-pass filter in the block diagram reduces the integrated noise at the MCP6S92’s output and serves as an anti-aliasing filter. This filter may be designed using Microchip’s FilterLab www.microchip.com. ® MCP6S91/2/3 Low-pass Filter MCP3201 3 12-bit OUT ADC PGA as an ADC driver. ® ...

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... PACKAGING INFORMATION 7.1 Package Marking Information 8-Lead PDIP (300 mil) (MCP6S91, MCP6S92) XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) (MCP6S91, MCP6S92) XXXXXXXX XXXXYYWW NNN 8-Lead MSOP (MCP6S91, MCP6S92) XXXXX YWWNNN 10-Lead MSOP (MCP6S93) XXXXX YWWNNN Legend: XX...X Customer specific information* ...

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... L .125 .130 .135 c .008 .012 .015 B1 .045 .058 .070 B .014 .018 .022 § eB .310 .370 .430 MCP6S91/2 MILLIMETERS MIN NOM MAX 8 2.54 3.56 3.94 4.32 2.92 3.30 3.68 0.38 7.62 7.94 8.26 6.10 6.35 6.60 9.14 9.46 9.78 3.18 3.30 3 ...

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... L .019 .025 .030 .008 .009 .010 B .013 .017 .020 MCP6S91/2/3 A2 MILLIMETERS MIN NOM MAX 8 1.27 1.35 1.55 1.75 1.32 1.42 1.55 0.10 0.18 0.25 5.79 6.02 6.20 3.71 3.91 3.99 4.80 4.90 5.00 0.25 0.38 ...

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... D .114 .118 .122 L .016 .022 .028 F .035 .037 .039 .004 .006 .008 B .010 .012 .016 7 7 MCP6S91/2/3 A2 MILLIMETERS* MIN NOM MAX 8 0.65 1.18 0.76 0.86 0.97 0.05 0.15 4.90 .5.08 4.67 2.90 3.00 3.10 2.90 3.00 3.10 0.40 0.55 0.70 ...

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... REF F φ 0° - 8° c .003 - .009 B .006 .009 .012 α 5° - 15° β 5° - 15° MCP6S91/2/3 α A2 MILLIMETERS* MIN NOM MAX 10 0.50 TYP 1.10 0.75 0.85 0.95 0.00 - 0.15 4.90 BSC 3.00 BSC 3.00 BSC 0.40 0.60 0.80 0.95 REF 0° ...

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... NOTES:  2004 Microchip Technology Inc. MCP6S91/2/3 DS21908A-page 36 ...

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... Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2004 Microchip Technology Inc. MCP6S91/2/3 . Examples: a) MCP6S91-E/P: One-channel PGA, PDIP package. b) MCP6S91-E/SN: One-channel PGA, SOIC package. c) ...

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... MCP6S91/2/3 NOTES: DS21908A-page 38  2004 Microchip Technology Inc. ...

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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

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