MCP1727-0802E/SN Microchip Technology, MCP1727-0802E/SN Datasheet - Page 22
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
MCP1727-0802E/SN
Manufacturer Part Number
MCP1727-0802E/SN
Description
1.5A CMOS LDO, Vout=0.8V, Extended Temp Range 8 SOIC 3.90mm (.150") TUBE
Manufacturer
Microchip Technology
Specifications of MCP1727-0802E/SN
Regulator Topology
Positive Fixed
Voltage - Output
0.8V
Voltage - Input
2.3 ~ 6 V
Voltage - Dropout (typical)
0.33V @ 1.5A
Number Of Regulators
1
Current - Output
1.5A (Min)
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Number Of Outputs
1
Polarity
Positive
Input Voltage Max
6 V
Output Voltage
0.8 V
Output Type
Fixed
Dropout Voltage (max)
0.55 V at 1.5 A
Output Current
1.5 A
Line Regulation
0.05 % / V
Load Regulation
0.5 %
Voltage Regulation Accuracy
2 %
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Limit (min)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
MCP1727
5.3.1.2
To estimate the internal junction temperature, the
calculated temperature rise is added to the ambient or
offset temperature. For this example, the worst-case
junction temperature is estimated below:
As you can see from the result, this application will be
operating very near the maximum operating junction
temperature of 125°C. The PCB layout for this
application is very important as it has a significant
impact on the junction-to-ambient thermal resistance
(Rθ
in this application.
5.3.1.3
From this table, you can see the difference in maximum
allowable power dissipation between the 3x3 DFN
package and the 8-pin SOIC package. This difference
is due to the exposed metal tab on the bottom of the
DFN package. The exposed tab of the DFN package
provides a very good thermal path from the die of the
LDO to the PCB. The PCB then acts like a heatsink,
providing more area to distribute the heat generated by
the LDO.
DS21999B-page 22
3x3DFN (41° C/W Rθ
SOIC8 (150°C/Watt Rθ
JA
P
P
P
P
) of the 3x3 DFN package, which is very important
D(MAX)
D(MAX)
D(MAX)
D(MAX)
T
T
T
J
J
J
Junction Temperature Estimate
Maximum Package Power
Dissipation at 60°C Ambient
Temperature
= T
= 63.14°C + 60.0°C
= 123.14°C
= (125°C – 60°C) / 41° C/W
= 1.585W
= (125°C – 60°C)/ 150° C/W
= 0.433W
JRISE
JA
+ T
JA
):
):
A(MAX)
5.4
C
Where:
For a delay of 300 ms:
C = 333.3E-09 * .300
C = 100E-09uF (0.1 μF)
=
I
ΔV
ΔT
C
•
C
DELAY
I
ΔT
------ -
ΔV
=
=
=
=
=
(
--------------------------------- -
140nA ΔT
Calculations (typical)
C
0.42V
C
C
140 nA typical.
time delay
C
0.42V typical
© 2007 Microchip Technology Inc.
DELAY
DELAY
DELAY
=
•
I
•
ΔT
------ -
ΔV
)
Capacitor
charging current,
threshold voltage,
=
333.3
×10
–
09
•
ΔT