LP3470IM5-2.63 National Semiconductor, LP3470IM5-2.63 Datasheet - Page 5

• Manufacturer Part Number: LP3470IM5-2.63
• Description: IC,VOLT DETECTOR,FIXED,+2.63V,CMOS,TSOP,5PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of LP3470IM5-2.63

• Rohs Compliant: NO

Functional Block Diagram
Application Information
Reset Timeout Period
The Reset Timeout Period (t
external capacitor (C
Ceramic chip capacitor rated at or above 10V is sufficient.
The Reset Timeout Period (t
following formula:
For example a C
no delay due to t
SRT should be left floating.
Reset Output
In applications like microprocessor (µP) systems, errors
might
power-down, or brownout conditions. It is imperative to
monitor the power supply voltage in order to prevent these
errors from occurring.
The LP3470 asserts a reset signal whenever the V
voltage is below a threshold (V
teed to be a logic low for V
reset threshold, the reset is kept asserted for a time period
(t
terval Reset goes to logic high. If a brownout condition oc-
curs (monitored voltage falls below the reset threshold minus
a small hysteresis), Reset goes low. When V
above the reset threshold, Reset remains low for a time pe-
riod t
RP
) programmed by an external capacitor (C
RP
occur
before going to logic high.
in
RP
t
1
RP
of 100 nF will achieve a t
is needed in a certain application, the pin
system
(ms) = 2000 x C
1
) connected to pin SRT of LP3470. A
CC
RP
RP
>
operation
RTH
) can be calculated using the
) is programmable using an
0.5V. Once V
) voltage. Reset is guaran-
1
(µF).
during
RP
CC
1
); after this in-
of 200 ms. If
exceeds the
CC
power-up,
CC
returns
supply
5
Pull-up Resistor Selection
The LP3470’s Reset output structure is a simple open-drain
N-channel MOSFET switch. A pull-up resistor (R
connected to V
R
output MOSFET (Q
than 680
to ensure a logic high while supplying all the leakage current
through the Reset pin. A resistor value of less than 68k sat-
isfies this condition. A typical pull-up resistor value of 20 k
is sufficient in most applications.
Negative-Going V
The LP3470 is relatively immune to short duration
negative-going V
ating Characteristics show the Maximum Transient Duration
vs. Negative Transient Amplitude (graph titled Transient Re-
jection), for which reset pulses are not generated. This graph
shows the maximum pulse width a negative-going V
sient may typically have without causing a reset pulse to be
issued. As the transient amplitude increases (i.e. goes far-
ther below the reset threshold), the maximum allowable
pulse width decreases. A 0.1 µF bypass capacitor mounted
close to V
1
should be large enough to limit the current through the
CC
guarantees this. R
provides additional transient immunity.
CC
CC
.
CC
1
) below 10 mA. A resistor value of more
transients (glitches). The Typical Oper-
Transients
1
should also be small enough
DS100016-3
1
www.national.com
) should be
CC
tran-