LM75CIMX-3 National Semiconductor, LM75CIMX-3 Datasheet - Page 11

• Manufacturer Part Number: LM75CIMX-3
• Description: IC,TEMPERATURE SENSOR,SOP,8PIN,PLASTIC
• Manufacturer: National Semiconductor

Specifications of LM75CIMX-3

• Rohs Compliant: NO

1.0 Functional Description
1.11 POINTER REGISTER
(Selects which registers will be read from or written to):
P0-P1: Register Select:
P2–P7: Must be kept zero.
1.12 TEMPERATURE REGISTER
D0–D6: Undefined
D7–D15: Temperature Data. One LSB = 0.5˚C. Two’s
complement format.
1.13 CONFIGURATION REGISTER
Power up default is with all bits “0” (zero).
D0: Shutdown: When set to 1 the LM75 goes to low power
shutdown mode.
D1: Comparator/Interrupt mode: 0 is Comparator mode, 1 is
Interrupt mode.
D2: O.S. Polarity: 0 is active low, 1 is active high. O.S. is an
open-drain output under all conditions.
D5–D7: These bits are used for production testing and must
be kept zero for normal operation.
1.14 T
D0–D6: Undefined
D7–D15: T
default is T
(Read Only):
(Read/Write):
(Read/Write):
MSB
MSB
D15
D15
HYST
D7
0
Bit 7
Bit 7
D14
D14
OS
HYST
AND T
= 80˚C, T
Or T
Bit 6
Bit 6
D13
D13
OS
OS
REGISTER
D6
0
HYST
Trip Temperature Data. Power up
Bit 5
Bit 5
D12
D12
= 75˚C.
Bit 4
Bit 4
D11
D11
P1
P7
0
0
1
1
0
D5
0
P0
Bit 3
Bit 3
D10
D10
0
1
0
1
P6
0
D4
Temperature (Read only) (Power-up default)
Configuration (Read/Write)
T
T
(Continued)
0
0
1
1
HYST
OS
Bit 2
Bit 2
P5
D9
D9
0
(Read/Write)
D3
(Read/Write)
0
1
0
1
D4
Fault Queue
Bit 1
Bit 1
P4
D8
1 (Power-up default)
2
4
6
D8
0
Number of Faults
11
Register
P3
LSB
LSB
0
D7
D7
D3–D4: Fault Queue: Number of faults necessary to detect
before setting O.S. output to avoid false tripping due to
noise. Faults are determind at the end of a conversion.
Conversions take about 100 ms, typically, to complete.
D3
P2
0
D6
D6
X
X
P1
Register
D5
D5
Select
Polarity
X
X
O.S.
D2
P0
D4
D4
X
X
D3
Cmp/Int
D3
X
X
D1
D2
D2
X
X
Shutdown
D1
D1
X
X
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D0
D0
D0
X
X