LM3671MF-1.2 National Semiconductor, LM3671MF-1.2 Datasheet - Page 17

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LM3671MF-1.2

Manufacturer Part Number
LM3671MF-1.2
Description
IC,SMPS CONTROLLER,VOLTAGE-MODE,TSOP,5PIN,PLASTIC
Manufacturer
National Semiconductor
Datasheet

Specifications of LM3671MF-1.2

Rohs Compliant
NO

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0
load current demanded at start-up. Typical start-up times with
a 10µF output capacitor and 300mA load is 400 µs and with
1mA load is 275µs.
LDO - LOW DROP OUT OPERATION
The LM3671-ADJ can operate at 100% duty cycle (no switch-
ing; PMOS switch completely on) for low drop out support of
the output voltage. In this way the output voltage will be con-
trolled down to the lowest possible input voltage. When the
device operates near 100% duty cycle, output voltage ripple
is approximately 25 mV.
The minimum input voltage needed to support the output volt-
age is
V
Application Information
OUTPUT VOLTAGE SELECTION FOR LM3671-ADJ
The output voltage of the adjustable parts can be pro-
grammed through the resistor network connected from V
to FB, then to GND. V
FB equal to 0.5V. The resistor from FB to GND (R2) should
be 200 kΩ to keep the current drawn through this network well
below the 16 µA quiescent current level (PFM mode) but large
enough that it is not susceptible to noise. If R2 is 200 kΩ, and
V
will be 2.5 µA. The output voltage of the adjustable parts
ranges from 1.1V to 3.3V.
The formula for output voltage selection is:
IN, MIN
• I
• R
• R
FB
is 0.5V, the current through the resistor feedback network
LOAD
DSON, PFET
INDUCTOR
= I
LOAD
* (R
DSON, PFET
OUT
Load current
Drain to source resistance of PFET
switch in the triode region
Inductor resistance
is adjusted to make the voltage at
+ R
INDUCTOR
) + V
OUT
OUT
17
For any output voltage greater than or equal to 1.1V, a zero
must be added around 45 kHz for stability. The formula for
calculation of C1 is:
For output voltages higher than 2.5V, a pole must be placed
at 45 kHz as well. If the pole and zero are at the same fre-
quency the formula for calculation of C2 is:
The formula for location of zero and pole frequency created
by adding C1 and C2 is given below. By adding C1, a zero as
well as a higher frequency pole is introduced.
See the "LM3671-ADJ configurations for various V
V
V
R1: feedback resistor from V
R2: feedback resistor from FB to GND
OUT
FB
: feedback voltage = 0.5V
: output voltage (volts)
OUT
to FB
www.national.com
OUT
" table.

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