LM2700MT-ADJ National Semiconductor, LM2700MT-ADJ Datasheet - Page 11

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LM2700MT-ADJ

Manufacturer Part Number
LM2700MT-ADJ
Description
DC/DC Converter IC
Manufacturer
National Semiconductor
Datasheet

Specifications of LM2700MT-ADJ

No. Of Pins
14
Peak Reflow Compatible (260 C)
No
Leaded Process Compatible
No
Package / Case
14-TSSOP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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0
Operation
gin can also be improved by adding C
in the section. The equation for A
additional equations required for the calculation:
where R
mum input voltage, g
tance found in the Electrical Characteristics table, and R
SON
the Typical Performance Characteristics section.
Application Information
is the value chosen from the graph "R
L
is the minimum load resistance, V
(Continued)
mc ) 0.072fs (in V/s)
m
is the error amplifier transconduc-
DC
C2
is given below with
as discussed earlier
FIGURE 3. 600 kHz operation, 8V output
DSON
IN
is the mini-
vs. V
IN
" in
D -
11
LAYOUT CONSIDERATIONS
The LM2700 uses two separate ground connections, PGND
for the driver and NMOS power device and AGND for the
sensitive analog control circuitry. The AGND and PGND pins
should be tied directly together at the package. The feed-
back and compensation networks should be connected di-
rectly to a dedicated analog ground plane and this ground
plane must connect to the AGND pin. If no analog ground
plane is available then the ground connections of the feed-
back and compensation networks must tie directly to the
AGND pin. Connecting these networks to the PGND can
inject noise into the system and effect performance.
The input bypass capacitor C
be placed close to the IC. This will reduce copper trace
resistance which effects input voltage ripple of the IC. For
additional input voltage filtering, a 100nF bypass capacitor
can be placed in parallel with C
shunt any high frequency noise to ground. The output ca-
pacitor, C
copper trace connections for the C
crease the series resistance, which directly effects output
voltage ripple. The feedback network, resistors R
R
inductor, to minimize copper trace connections that can in-
ject noise into the system. Trace connections made to the
inductor and schottky diode should be minimized to reduce
power dissipation and increase overall efficiency. For more
detail on switching power supply layout considerations see
Application Note AN-1149: Layout Guidelines for Switching
Power Supplies.
FB2
, should be kept close to the FB pin, and away from the
OUT
, should also be placed close to the IC. Any
IN
, as shown in Figure 3, must
IN
20012331
, close to the V
OUT
capacitor can in-
www.national.com
IN
FB1
pin, to
and

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